Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	15324537	0	0
ctrl_rd_A	2147483647	361434	0	0
intr_enable_rd_A	2147483647	321592	0	0
ovrd_rd_A	2147483647	360618	0	0
timeout_ctrl_rd_A	2147483647	357011	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15324537	0	0
T14	456367	156294	0	0
T15	0	96285	0	0
T18	0	165975	0	0
T19	0	301261	0	0
T20	115171	0	0	0
T21	416677	0	0	0
T24	2871	0	0	0
T27	423064	0	0	0
T28	0	190293	0	0
T29	0	50186	0	0
T30	0	196835	0	0
T31	0	58197	0	0
T32	0	184675	0	0
T33	0	117557	0	0
T34	130736	0	0	0
T35	43208	0	0	0
T36	367836	0	0	0
T37	865407	0	0	0
T38	129497	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	361434	0	0
T15	387702	10900	0	0
T18	714778	17836	0	0
T33	0	5041	0	0
T42	104456	0	0	0
T54	0	5178	0	0
T55	0	29265	0	0
T102	0	16203	0	0
T103	0	13248	0	0
T104	0	6822	0	0
T105	0	7187	0	0
T106	0	13949	0	0
T107	988768	0	0	0
T108	52775	0	0	0
T109	274190	0	0	0
T110	651958	0	0	0
T111	188083	0	0	0
T112	164794	0	0	0
T113	25410	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	321592	0	0
T15	387702	9916	0	0
T18	714778	16137	0	0
T33	0	4744	0	0
T42	104456	0	0	0
T54	0	4569	0	0
T55	0	25736	0	0
T102	0	14773	0	0
T103	0	11298	0	0
T104	0	5843	0	0
T105	0	6515	0	0
T107	988768	0	0	0
T108	52775	0	0	0
T109	274190	0	0	0
T110	651958	0	0	0
T111	188083	0	0	0
T112	164794	0	0	0
T113	25410	0	0	0
T114	0	25	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	360618	0	0
T15	387702	10883	0	0
T18	714778	18662	0	0
T33	0	5432	0	0
T42	104456	0	0	0
T54	0	5278	0	0
T55	0	29039	0	0
T102	0	17012	0	0
T103	0	13066	0	0
T104	0	6773	0	0
T105	0	7085	0	0
T106	0	13351	0	0
T107	988768	0	0	0
T108	52775	0	0	0
T109	274190	0	0	0
T110	651958	0	0	0
T111	188083	0	0	0
T112	164794	0	0	0
T113	25410	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	357011	0	0
T15	387702	10323	0	0
T18	714778	17653	0	0
T33	0	5353	0	0
T42	104456	0	0	0
T54	0	5210	0	0
T55	0	28757	0	0
T102	0	16528	0	0
T103	0	13137	0	0
T104	0	6883	0	0
T105	0	6957	0	0
T106	0	13985	0	0
T107	988768	0	0	0
T108	52775	0	0	0
T109	274190	0	0	0
T110	651958	0	0	0
T111	188083	0	0	0
T112	164794	0	0	0
T113	25410	0	0	0