Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	79178990	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

28559557

1

T1

11914

T2

52161

T3

82

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	97730505	1			T1	186811		T2	248001		T3	7465
values[0x0]	4729477	1			T1	2618		T2	3003		T3	87
values[0x1]	5278565	1			T1	2642		T2	3127		T3	68

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	54779544	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

52959003

1

T1

69664

T2

111451

T3

2554

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	399319	1			T1	754		T2	963		T5	1665
valid_sources[0x01]	420794	1			T1	726		T2	1007		T5	1658
valid_sources[0x02]	548872	1			T1	759		T2	983		T5	1789
valid_sources[0x03]	406501	1			T1	765		T2	944		T5	1780
valid_sources[0x04]	548340	1			T1	756		T2	946		T5	1458
valid_sources[0x05]	393574	1			T1	688		T2	1095		T5	1798
valid_sources[0x06]	416989	1			T1	730		T2	896		T5	1605
valid_sources[0x07]	397508	1			T1	705		T2	969		T5	1741
valid_sources[0x08]	386884	1			T1	722		T2	1052		T5	1831
valid_sources[0x09]	425067	1			T1	729		T2	998		T5	1622
valid_sources[0x0a]	412602	1			T1	760		T2	1084		T5	1729
valid_sources[0x0b]	406535	1			T1	779		T2	962		T5	1446
valid_sources[0x0c]	414631	1			T1	724		T2	1047		T5	1675
valid_sources[0x0d]	446737	1			T1	750		T2	941		T5	1654
valid_sources[0x0e]	393754	1			T1	757		T2	1020		T5	1670
valid_sources[0x0f]	393150	1			T1	724		T2	921		T5	1512
valid_sources[0x10]	401095	1			T1	702		T2	948		T5	1503
valid_sources[0x11]	418300	1			T1	730		T2	959		T5	1559
valid_sources[0x12]	409240	1			T1	766		T2	1041		T5	1862
valid_sources[0x13]	398171	1			T1	742		T2	997		T5	1696
valid_sources[0x14]	404132	1			T1	744		T2	979		T5	1565
valid_sources[0x15]	491728	1			T1	750		T2	916		T5	1609
valid_sources[0x16]	449911	1			T1	727		T2	956		T5	1645
valid_sources[0x17]	406379	1			T1	721		T2	1051		T5	1497
valid_sources[0x18]	404549	1			T1	751		T2	1008		T5	1746
valid_sources[0x19]	474471	1			T1	702		T2	1035		T5	1779
valid_sources[0x1a]	391372	1			T1	782		T2	1000		T5	1549
valid_sources[0x1b]	444597	1			T1	775		T2	868		T5	1508
valid_sources[0x1c]	395139	1			T1	803		T2	1031		T5	1627
valid_sources[0x1d]	404365	1			T1	736		T2	998		T5	1596
valid_sources[0x1e]	404279	1			T1	760		T2	969		T5	1665
valid_sources[0x1f]	405805	1			T1	737		T2	980		T5	1597
valid_sources[0x20]	429035	1			T1	775		T2	1019		T5	1605
valid_sources[0x21]	430701	1			T1	755		T2	938		T5	1472
valid_sources[0x22]	405890	1			T1	747		T2	970		T5	1422
valid_sources[0x23]	405207	1			T1	754		T2	1011		T5	1679
valid_sources[0x24]	401577	1			T1	747		T2	964		T5	1640
valid_sources[0x25]	397657	1			T1	691		T2	899		T5	1791
valid_sources[0x26]	409979	1			T1	724		T2	875		T5	1726
valid_sources[0x27]	396311	1			T1	716		T2	977		T5	1687
valid_sources[0x28]	439927	1			T1	765		T2	955		T5	1565
valid_sources[0x29]	409216	1			T1	776		T2	1033		T5	1771
valid_sources[0x2a]	396667	1			T1	737		T2	993		T5	1636
valid_sources[0x2b]	391278	1			T1	680		T2	944		T5	1670
valid_sources[0x2c]	387312	1			T1	794		T2	1014		T5	1617
valid_sources[0x2d]	395036	1			T1	732		T2	1024		T5	1782
valid_sources[0x2e]	425408	1			T1	719		T2	1006		T5	1777
valid_sources[0x2f]	393076	1			T1	723		T2	978		T5	1813
valid_sources[0x30]	397097	1			T1	765		T2	912		T5	1635
valid_sources[0x31]	465317	1			T1	748		T2	1045		T5	1806
valid_sources[0x32]	411861	1			T1	765		T2	1079		T5	1467
valid_sources[0x33]	413426	1			T1	723		T2	1073		T5	1690
valid_sources[0x34]	407130	1			T1	749		T2	942		T5	1713
valid_sources[0x35]	409026	1			T1	778		T2	942		T5	1801
valid_sources[0x36]	402815	1			T1	759		T2	1006		T5	1749
valid_sources[0x37]	517935	1			T1	754		T2	944		T5	1720
valid_sources[0x38]	461508	1			T1	762		T2	947		T5	1771
valid_sources[0x39]	400061	1			T1	692		T2	966		T5	1814
valid_sources[0x3a]	406971	1			T1	778		T2	985		T5	1626
valid_sources[0x3b]	447970	1			T1	782		T2	1049		T5	1875
valid_sources[0x3c]	511770	1			T1	738		T2	1008		T5	1773
valid_sources[0x3d]	412549	1			T1	748		T2	994		T5	1712
valid_sources[0x3e]	417708	1			T1	800		T2	992		T5	1528
valid_sources[0x3f]	442235	1			T1	755		T2	978		T5	1762
valid_sources[0x40]	388610	1			T1	724		T2	1026		T5	1602
valid_sources[0x41]	401273	1			T1	773		T2	981		T5	1639
valid_sources[0x42]	408219	1			T1	760		T2	1040		T5	1660
valid_sources[0x43]	394601	1			T1	776		T2	955		T5	1643
valid_sources[0x44]	414254	1			T1	768		T2	957		T5	1645
valid_sources[0x45]	433279	1			T1	808		T2	981		T5	1513
valid_sources[0x46]	408219	1			T1	744		T2	953		T5	1568
valid_sources[0x47]	403658	1			T1	696		T2	985		T5	1787
valid_sources[0x48]	483691	1			T1	769		T2	992		T5	1685
valid_sources[0x49]	400322	1			T1	720		T2	1015		T5	1836
valid_sources[0x4a]	410287	1			T1	792		T2	987		T5	1602
valid_sources[0x4b]	391437	1			T1	769		T2	968		T5	1472
valid_sources[0x4c]	418769	1			T1	768		T2	950		T5	1783
valid_sources[0x4d]	408616	1			T1	719		T2	943		T5	1809
valid_sources[0x4e]	567325	1			T1	767		T2	960		T5	1559
valid_sources[0x4f]	424563	1			T1	703		T2	1031		T5	1594
valid_sources[0x50]	413512	1			T1	715		T2	1050		T5	1765
valid_sources[0x51]	396550	1			T1	741		T2	1036		T5	1775
valid_sources[0x52]	451077	1			T1	720		T2	1059		T5	1770
valid_sources[0x53]	419418	1			T1	736		T2	1004		T5	1650
valid_sources[0x54]	388058	1			T1	721		T2	937		T5	1824
valid_sources[0x55]	416617	1			T1	794		T2	1016		T5	1662
valid_sources[0x56]	419080	1			T1	762		T2	1122		T5	1612
valid_sources[0x57]	407987	1			T1	738		T2	1014		T5	1640
valid_sources[0x58]	390765	1			T1	760		T2	990		T5	1592
valid_sources[0x59]	410391	1			T1	756		T2	988		T5	1883
valid_sources[0x5a]	440193	1			T1	751		T2	989		T5	1678
valid_sources[0x5b]	428314	1			T1	703		T2	1014		T5	1684
valid_sources[0x5c]	495494	1			T1	694		T2	1031		T5	1683
valid_sources[0x5d]	417923	1			T1	678		T2	961		T5	1752
valid_sources[0x5e]	389283	1			T1	772		T2	1051		T5	1612
valid_sources[0x5f]	410258	1			T1	802		T2	961		T5	1918
valid_sources[0x60]	456478	1			T1	723		T2	972		T5	1582
valid_sources[0x61]	397545	1			T1	687		T2	1066		T5	1497
valid_sources[0x62]	407127	1			T1	808		T2	1022		T5	1690
valid_sources[0x63]	409136	1			T1	698		T2	1019		T5	1532
valid_sources[0x64]	390222	1			T1	796		T2	1000		T5	1707
valid_sources[0x65]	400820	1			T1	748		T2	1053		T5	1535
valid_sources[0x66]	401091	1			T1	796		T2	1005		T5	1724
valid_sources[0x67]	397711	1			T1	778		T2	945		T5	1800
valid_sources[0x68]	400630	1			T1	756		T2	994		T5	1802
valid_sources[0x69]	509574	1			T1	731		T2	984		T5	1619
valid_sources[0x6a]	420488	1			T1	764		T2	998		T5	1822
valid_sources[0x6b]	401510	1			T1	692		T2	1008		T5	1685
valid_sources[0x6c]	396616	1			T1	737		T2	1008		T5	1712
valid_sources[0x6d]	398556	1			T1	742		T2	973		T5	1697
valid_sources[0x6e]	427374	1			T1	807		T2	979		T5	1791
valid_sources[0x6f]	454753	1			T1	817		T2	976		T5	1573
valid_sources[0x70]	466401	1			T1	792		T2	923		T5	1634
valid_sources[0x71]	417912	1			T1	720		T2	1022		T5	1813
valid_sources[0x72]	411399	1			T1	742		T2	997		T5	1767
valid_sources[0x73]	396847	1			T1	775		T2	1039		T5	1590
valid_sources[0x74]	404158	1			T1	799		T2	1028		T5	1982
valid_sources[0x75]	400443	1			T1	728		T2	974		T5	1807
valid_sources[0x76]	412862	1			T1	719		T2	1089		T5	1528
valid_sources[0x77]	408835	1			T1	741		T2	980		T5	1471
valid_sources[0x78]	456805	1			T1	819		T2	917		T5	1793
valid_sources[0x79]	397101	1			T1	737		T2	920		T5	1882
valid_sources[0x7a]	419354	1			T1	746		T2	986		T5	1693
valid_sources[0x7b]	427048	1			T1	803		T2	962		T5	1686
valid_sources[0x7c]	494211	1			T1	766		T2	910		T5	1704
valid_sources[0x7d]	405228	1			T1	818		T2	1001		T5	1667
valid_sources[0x7e]	512088	1			T1	735		T2	999		T5	1628
valid_sources[0x7f]	409293	1			T1	750		T2	1035		T5	1656
valid_sources[0x80]	448125	1			T1	738		T2	912		T5	1577

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19716330

1

T1

10563

T2

50603

T3

36

values[0x0]

all_enables

biggest_size

4450652

1

T1

923

T2

999

T3

35

values[0x1]

all_enables

biggest_size

4392575

1

T1

428

T2

559

T3

11