Line Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Module :
prim_fifo_sync
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (8'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_fifo_sync
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
350434 |
320433 |
0 |
0 |
T2 |
1077626 |
600408 |
0 |
0 |
T3 |
956890 |
813543 |
0 |
0 |
T4 |
808216 |
1159031 |
0 |
0 |
T5 |
1781034 |
656227 |
0 |
0 |
T6 |
1628412 |
494929 |
0 |
0 |
T7 |
1498176 |
1045381 |
0 |
0 |
T8 |
352938 |
1049913 |
0 |
0 |
T9 |
50066 |
758 |
0 |
0 |
T10 |
1072966 |
337573 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
350434 |
350414 |
0 |
0 |
T2 |
1077626 |
1077614 |
0 |
0 |
T3 |
956890 |
956876 |
0 |
0 |
T4 |
808216 |
808202 |
0 |
0 |
T5 |
1781034 |
1780898 |
0 |
0 |
T6 |
1628412 |
1628296 |
0 |
0 |
T7 |
1498176 |
1498146 |
0 |
0 |
T8 |
352938 |
352922 |
0 |
0 |
T9 |
50066 |
49914 |
0 |
0 |
T10 |
1072966 |
1072944 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
350434 |
350414 |
0 |
0 |
T2 |
1077626 |
1077614 |
0 |
0 |
T3 |
956890 |
956876 |
0 |
0 |
T4 |
808216 |
808202 |
0 |
0 |
T5 |
1781034 |
1780898 |
0 |
0 |
T6 |
1628412 |
1628296 |
0 |
0 |
T7 |
1498176 |
1498146 |
0 |
0 |
T8 |
352938 |
352922 |
0 |
0 |
T9 |
50066 |
49914 |
0 |
0 |
T10 |
1072966 |
1072944 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
350434 |
350414 |
0 |
0 |
T2 |
1077626 |
1077614 |
0 |
0 |
T3 |
956890 |
956876 |
0 |
0 |
T4 |
808216 |
808202 |
0 |
0 |
T5 |
1781034 |
1780898 |
0 |
0 |
T6 |
1628412 |
1628296 |
0 |
0 |
T7 |
1498176 |
1498146 |
0 |
0 |
T8 |
352938 |
352922 |
0 |
0 |
T9 |
50066 |
49914 |
0 |
0 |
T10 |
1072966 |
1072944 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
350434 |
320433 |
0 |
0 |
T2 |
1077626 |
600408 |
0 |
0 |
T3 |
956890 |
813543 |
0 |
0 |
T4 |
808216 |
1159031 |
0 |
0 |
T5 |
1781034 |
656227 |
0 |
0 |
T6 |
1628412 |
494929 |
0 |
0 |
T7 |
1498176 |
1045381 |
0 |
0 |
T8 |
352938 |
1049913 |
0 |
0 |
T9 |
50066 |
758 |
0 |
0 |
T10 |
1072966 |
337573 |
0 |
0 |
Line Coverage for Instance : tb.dut.uart_core.u_uart_txfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.uart_core.u_uart_txfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (8'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.uart_core.u_uart_txfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.uart_core.u_uart_txfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1915249024 |
0 |
0 |
T1 |
175217 |
164073 |
0 |
0 |
T2 |
538813 |
538446 |
0 |
0 |
T3 |
478445 |
188370 |
0 |
0 |
T4 |
404108 |
267607 |
0 |
0 |
T5 |
890517 |
646729 |
0 |
0 |
T6 |
814206 |
262348 |
0 |
0 |
T7 |
749088 |
202644 |
0 |
0 |
T8 |
176469 |
845549 |
0 |
0 |
T9 |
25033 |
10 |
0 |
0 |
T10 |
536483 |
208470 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
175217 |
175207 |
0 |
0 |
T2 |
538813 |
538807 |
0 |
0 |
T3 |
478445 |
478438 |
0 |
0 |
T4 |
404108 |
404101 |
0 |
0 |
T5 |
890517 |
890449 |
0 |
0 |
T6 |
814206 |
814148 |
0 |
0 |
T7 |
749088 |
749073 |
0 |
0 |
T8 |
176469 |
176461 |
0 |
0 |
T9 |
25033 |
24957 |
0 |
0 |
T10 |
536483 |
536472 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
175217 |
175207 |
0 |
0 |
T2 |
538813 |
538807 |
0 |
0 |
T3 |
478445 |
478438 |
0 |
0 |
T4 |
404108 |
404101 |
0 |
0 |
T5 |
890517 |
890449 |
0 |
0 |
T6 |
814206 |
814148 |
0 |
0 |
T7 |
749088 |
749073 |
0 |
0 |
T8 |
176469 |
176461 |
0 |
0 |
T9 |
25033 |
24957 |
0 |
0 |
T10 |
536483 |
536472 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
175217 |
175207 |
0 |
0 |
T2 |
538813 |
538807 |
0 |
0 |
T3 |
478445 |
478438 |
0 |
0 |
T4 |
404108 |
404101 |
0 |
0 |
T5 |
890517 |
890449 |
0 |
0 |
T6 |
814206 |
814148 |
0 |
0 |
T7 |
749088 |
749073 |
0 |
0 |
T8 |
176469 |
176461 |
0 |
0 |
T9 |
25033 |
24957 |
0 |
0 |
T10 |
536483 |
536472 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1915249024 |
0 |
0 |
T1 |
175217 |
164073 |
0 |
0 |
T2 |
538813 |
538446 |
0 |
0 |
T3 |
478445 |
188370 |
0 |
0 |
T4 |
404108 |
267607 |
0 |
0 |
T5 |
890517 |
646729 |
0 |
0 |
T6 |
814206 |
262348 |
0 |
0 |
T7 |
749088 |
202644 |
0 |
0 |
T8 |
176469 |
845549 |
0 |
0 |
T9 |
25033 |
10 |
0 |
0 |
T10 |
536483 |
208470 |
0 |
0 |
Line Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T8,T11 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T3,T8,T11 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (8'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
660399981 |
0 |
0 |
T1 |
175217 |
156360 |
0 |
0 |
T2 |
538813 |
61962 |
0 |
0 |
T3 |
478445 |
625173 |
0 |
0 |
T4 |
404108 |
891424 |
0 |
0 |
T5 |
890517 |
9498 |
0 |
0 |
T6 |
814206 |
232581 |
0 |
0 |
T7 |
749088 |
842737 |
0 |
0 |
T8 |
176469 |
204364 |
0 |
0 |
T9 |
25033 |
748 |
0 |
0 |
T10 |
536483 |
129103 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
175217 |
175207 |
0 |
0 |
T2 |
538813 |
538807 |
0 |
0 |
T3 |
478445 |
478438 |
0 |
0 |
T4 |
404108 |
404101 |
0 |
0 |
T5 |
890517 |
890449 |
0 |
0 |
T6 |
814206 |
814148 |
0 |
0 |
T7 |
749088 |
749073 |
0 |
0 |
T8 |
176469 |
176461 |
0 |
0 |
T9 |
25033 |
24957 |
0 |
0 |
T10 |
536483 |
536472 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
175217 |
175207 |
0 |
0 |
T2 |
538813 |
538807 |
0 |
0 |
T3 |
478445 |
478438 |
0 |
0 |
T4 |
404108 |
404101 |
0 |
0 |
T5 |
890517 |
890449 |
0 |
0 |
T6 |
814206 |
814148 |
0 |
0 |
T7 |
749088 |
749073 |
0 |
0 |
T8 |
176469 |
176461 |
0 |
0 |
T9 |
25033 |
24957 |
0 |
0 |
T10 |
536483 |
536472 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
175217 |
175207 |
0 |
0 |
T2 |
538813 |
538807 |
0 |
0 |
T3 |
478445 |
478438 |
0 |
0 |
T4 |
404108 |
404101 |
0 |
0 |
T5 |
890517 |
890449 |
0 |
0 |
T6 |
814206 |
814148 |
0 |
0 |
T7 |
749088 |
749073 |
0 |
0 |
T8 |
176469 |
176461 |
0 |
0 |
T9 |
25033 |
24957 |
0 |
0 |
T10 |
536483 |
536472 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
660399981 |
0 |
0 |
T1 |
175217 |
156360 |
0 |
0 |
T2 |
538813 |
61962 |
0 |
0 |
T3 |
478445 |
625173 |
0 |
0 |
T4 |
404108 |
891424 |
0 |
0 |
T5 |
890517 |
9498 |
0 |
0 |
T6 |
814206 |
232581 |
0 |
0 |
T7 |
749088 |
842737 |
0 |
0 |
T8 |
176469 |
204364 |
0 |
0 |
T9 |
25033 |
748 |
0 |
0 |
T10 |
536483 |
129103 |
0 |
0 |