Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14550826	0	0
ctrl_rd_A	2147483647	263603	0	0
intr_enable_rd_A	2147483647	234375	0	0
ovrd_rd_A	2147483647	265474	0	0
timeout_ctrl_rd_A	2147483647	264535	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14550826	0	0
T7	749088	176934	0	0
T8	176469	0	0	0
T9	25033	0	0	0
T10	536483	222349	0	0
T11	234327	0	0	0
T12	244124	0	0	0
T15	120078	0	0	0
T18	0	175778	0	0
T19	66375	0	0	0
T26	0	456496	0	0
T27	0	85222	0	0
T28	0	32171	0	0
T29	0	17383	0	0
T30	0	576913	0	0
T31	0	119701	0	0
T32	0	210885	0	0
T33	243137	0	0	0
T34	842606	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	263603	0	0
T7	749088	19911	0	0
T8	176469	0	0	0
T9	25033	0	0	0
T10	536483	0	0	0
T11	234327	0	0	0
T12	244124	0	0	0
T15	120078	0	0	0
T19	66375	0	0	0
T28	0	3442	0	0
T29	0	2053	0	0
T31	0	11654	0	0
T33	243137	0	0	0
T34	842606	0	0	0
T96	0	7876	0	0
T97	0	2677	0	0
T98	0	10455	0	0
T99	0	2937	0	0
T100	0	4484	0	0
T101	0	13754	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	234375	0	0
T7	749088	17888	0	0
T8	176469	0	0	0
T9	25033	0	0	0
T10	536483	0	0	0
T11	234327	0	0	0
T12	244124	0	0	0
T15	120078	0	0	0
T19	66375	0	0	0
T28	0	2846	0	0
T29	0	1792	0	0
T31	0	10766	0	0
T33	243137	0	0	0
T34	842606	0	0	0
T96	0	7304	0	0
T97	0	2500	0	0
T98	0	9152	0	0
T99	0	2459	0	0
T100	0	4248	0	0
T101	0	11710	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	265474	0	0
T7	749088	20303	0	0
T8	176469	0	0	0
T9	25033	0	0	0
T10	536483	0	0	0
T11	234327	0	0	0
T12	244124	0	0	0
T15	120078	0	0	0
T19	66375	0	0	0
T28	0	3413	0	0
T29	0	2168	0	0
T31	0	12318	0	0
T33	243137	0	0	0
T34	842606	0	0	0
T96	0	8175	0	0
T97	0	2737	0	0
T98	0	9963	0	0
T99	0	2889	0	0
T100	0	4558	0	0
T101	0	14068	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	264535	0	0
T7	749088	20467	0	0
T8	176469	0	0	0
T9	25033	0	0	0
T10	536483	0	0	0
T11	234327	0	0	0
T12	244124	0	0	0
T15	120078	0	0	0
T19	66375	0	0	0
T28	0	3390	0	0
T29	0	1980	0	0
T31	0	12076	0	0
T33	243137	0	0	0
T34	842606	0	0	0
T96	0	8053	0	0
T97	0	2585	0	0
T98	0	10045	0	0
T99	0	2919	0	0
T100	0	4587	0	0
T101	0	13255	0	0