Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	15635894	0	0
ctrl_rd_A	2147483647	319681	0	0
intr_enable_rd_A	2147483647	282824	0	0
ovrd_rd_A	2147483647	317411	0	0
timeout_ctrl_rd_A	2147483647	317840	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15635894	0	0
T12	809480	338416	0	0
T13	926075	0	0	0
T14	251127	0	0	0
T18	100244	0	0	0
T19	168020	0	0	0
T20	0	40777	0	0
T21	0	55025	0	0
T22	1061	0	0	0
T28	0	291220	0	0
T29	0	202970	0	0
T30	0	132150	0	0
T31	0	117260	0	0
T32	0	349924	0	0
T33	0	80083	0	0
T34	0	88909	0	0
T35	176685	0	0	0
T36	608248	0	0	0
T37	430239	0	0	0
T38	934250	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	319681	0	0
T21	173608	3279	0	0
T31	0	13832	0	0
T34	0	3623	0	0
T42	0	3596	0	0
T53	0	5351	0	0
T119	0	3557	0	0
T120	0	11070	0	0
T121	0	5285	0	0
T122	0	4466	0	0
T123	0	5120	0	0
T124	186067	0	0	0
T125	505339	0	0	0
T126	933218	0	0	0
T127	268245	0	0	0
T128	984	0	0	0
T129	942	0	0	0
T130	296375	0	0	0
T131	169879	0	0	0
T132	288635	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	282824	0	0
T21	0	2846	0	0
T31	0	12132	0	0
T34	0	3240	0	0
T42	0	3162	0	0
T98	105314	11	0	0
T119	0	3022	0	0
T120	0	10369	0	0
T121	0	4660	0	0
T122	0	3849	0	0
T123	0	4544	0	0
T133	16566	0	0	0
T134	133854	0	0	0
T135	267078	0	0	0
T136	97570	0	0	0
T137	663562	0	0	0
T138	950765	0	0	0
T139	152518	0	0	0
T140	88318	0	0	0
T141	352249	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	317411	0	0
T21	173608	3164	0	0
T31	0	13787	0	0
T34	0	3644	0	0
T42	0	3684	0	0
T53	0	5176	0	0
T119	0	3488	0	0
T120	0	11680	0	0
T121	0	5405	0	0
T122	0	4643	0	0
T123	0	5351	0	0
T124	186067	0	0	0
T125	505339	0	0	0
T126	933218	0	0	0
T127	268245	0	0	0
T128	984	0	0	0
T129	942	0	0	0
T130	296375	0	0	0
T131	169879	0	0	0
T132	288635	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	317840	0	0
T21	173608	3106	0	0
T31	0	13768	0	0
T34	0	3662	0	0
T42	0	3582	0	0
T53	0	5424	0	0
T119	0	3357	0	0
T120	0	11004	0	0
T121	0	5366	0	0
T122	0	4508	0	0
T123	0	5341	0	0
T124	186067	0	0	0
T125	505339	0	0	0
T126	933218	0	0	0
T127	268245	0	0	0
T128	984	0	0	0
T129	942	0	0	0
T130	296375	0	0	0
T131	169879	0	0	0
T132	288635	0	0	0