Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	73134238	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

27985046

1

T1

60200

T2

21

T3

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	90583286	1			T1	186148		T2	2869		T3	1713
values[0x0]	4975783	1			T1	260		T2	12		T3	8
values[0x1]	5560215	1			T1	251		T2	14		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	50492935	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

50626349

1

T1

94411

T2

1458

T3

513

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	401139	1			T1	425		T2	13		T3	3
valid_sources[0x01]	387270	1			T1	975		T2	13		T3	16
valid_sources[0x02]	391132	1			T1	812		T2	15		T3	12
valid_sources[0x03]	405015	1			T1	617		T2	17		T3	1
valid_sources[0x04]	374547	1			T1	986		T2	5		T3	8
valid_sources[0x05]	397535	1			T1	429		T2	19		T3	7
valid_sources[0x06]	433867	1			T1	974		T2	10		T3	7
valid_sources[0x07]	385489	1			T1	841		T2	10		T3	4
valid_sources[0x08]	381564	1			T1	390		T2	10		T3	5
valid_sources[0x09]	422794	1			T1	779		T2	8		T4	4
valid_sources[0x0a]	372684	1			T1	719		T2	12		T3	3
valid_sources[0x0b]	388792	1			T1	858		T2	10		T3	6
valid_sources[0x0c]	407624	1			T1	1011		T2	13		T3	1
valid_sources[0x0d]	395961	1			T1	494		T2	9		T3	21
valid_sources[0x0e]	402090	1			T1	510		T2	14		T3	15
valid_sources[0x0f]	363095	1			T1	435		T2	12		T3	5
valid_sources[0x10]	440494	1			T1	513		T2	8		T3	22
valid_sources[0x11]	394262	1			T1	713		T2	9		T3	8
valid_sources[0x12]	404560	1			T1	665		T2	8		T3	2
valid_sources[0x13]	393003	1			T1	432		T2	8		T3	10
valid_sources[0x14]	371006	1			T1	734		T2	12		T3	2
valid_sources[0x15]	373348	1			T1	1245		T2	10		T4	8
valid_sources[0x16]	395375	1			T1	468		T2	5		T3	1
valid_sources[0x17]	379874	1			T1	416		T2	7		T3	21
valid_sources[0x18]	453582	1			T1	953		T2	16		T3	7
valid_sources[0x19]	436668	1			T1	869		T2	12		T3	7
valid_sources[0x1a]	416233	1			T1	542		T2	22		T3	6
valid_sources[0x1b]	403753	1			T1	401		T2	18		T4	11
valid_sources[0x1c]	391954	1			T1	874		T2	15		T3	6
valid_sources[0x1d]	374997	1			T1	437		T2	21		T3	16
valid_sources[0x1e]	397537	1			T1	446		T2	6		T3	5
valid_sources[0x1f]	390979	1			T1	812		T2	11		T4	3
valid_sources[0x20]	367838	1			T1	490		T2	30		T3	5
valid_sources[0x21]	397274	1			T1	1390		T2	11		T3	2
valid_sources[0x22]	421078	1			T1	378		T2	9		T3	24
valid_sources[0x23]	378579	1			T1	912		T2	15		T3	3
valid_sources[0x24]	380310	1			T1	372		T2	3		T3	11
valid_sources[0x25]	387969	1			T1	862		T2	15		T3	3
valid_sources[0x26]	490277	1			T1	921		T2	5		T3	5
valid_sources[0x27]	430636	1			T1	528		T2	13		T3	1
valid_sources[0x28]	379940	1			T1	763		T2	10		T3	10
valid_sources[0x29]	384553	1			T1	199		T2	14		T3	8
valid_sources[0x2a]	367680	1			T1	386		T2	11		T4	3
valid_sources[0x2b]	383899	1			T1	508		T2	11		T4	7
valid_sources[0x2c]	402942	1			T1	667		T2	13		T4	8
valid_sources[0x2d]	468892	1			T1	1033		T2	7		T3	3
valid_sources[0x2e]	372737	1			T1	884		T2	7		T3	14
valid_sources[0x2f]	397370	1			T1	575		T2	12		T3	6
valid_sources[0x30]	397637	1			T1	435		T2	9		T3	2
valid_sources[0x31]	366686	1			T1	689		T2	12		T3	8
valid_sources[0x32]	389710	1			T1	778		T2	11		T3	10
valid_sources[0x33]	382956	1			T1	950		T2	12		T3	6
valid_sources[0x34]	378927	1			T1	744		T2	12		T3	16
valid_sources[0x35]	392725	1			T1	875		T2	6		T3	11
valid_sources[0x36]	369323	1			T1	862		T2	16		T3	6
valid_sources[0x37]	393482	1			T1	1146		T2	15		T3	4
valid_sources[0x38]	463444	1			T1	936		T2	14		T3	8
valid_sources[0x39]	386218	1			T1	567		T2	8		T3	8
valid_sources[0x3a]	390974	1			T1	908		T2	8		T3	12
valid_sources[0x3b]	378465	1			T1	213		T2	11		T3	11
valid_sources[0x3c]	380802	1			T1	1054		T2	5		T3	9
valid_sources[0x3d]	395849	1			T1	907		T2	4		T3	4
valid_sources[0x3e]	396696	1			T1	728		T2	11		T3	5
valid_sources[0x3f]	392135	1			T1	635		T2	10		T3	8
valid_sources[0x40]	374042	1			T1	538		T2	6		T3	18
valid_sources[0x41]	419961	1			T1	864		T2	13		T3	11
valid_sources[0x42]	376553	1			T1	945		T2	10		T3	12
valid_sources[0x43]	396249	1			T1	808		T2	11		T3	2
valid_sources[0x44]	417558	1			T1	665		T2	11		T3	6
valid_sources[0x45]	406217	1			T1	916		T2	12		T3	8
valid_sources[0x46]	423018	1			T1	1129		T2	5		T3	1
valid_sources[0x47]	401407	1			T1	477		T2	7		T3	17
valid_sources[0x48]	501132	1			T1	355		T2	16		T3	7
valid_sources[0x49]	390795	1			T1	359		T2	16		T3	9
valid_sources[0x4a]	407273	1			T1	587		T2	14		T4	16
valid_sources[0x4b]	395744	1			T1	538		T2	18		T3	1
valid_sources[0x4c]	415744	1			T1	681		T2	14		T3	19
valid_sources[0x4d]	393425	1			T1	603		T2	15		T3	8
valid_sources[0x4e]	373522	1			T1	671		T2	10		T3	4
valid_sources[0x4f]	414713	1			T1	427		T2	5		T3	18
valid_sources[0x50]	465211	1			T1	774		T2	12		T3	3
valid_sources[0x51]	367188	1			T1	763		T2	7		T3	7
valid_sources[0x52]	397418	1			T1	968		T2	14		T3	14
valid_sources[0x53]	414138	1			T1	744		T2	10		T3	14
valid_sources[0x54]	374707	1			T1	618		T2	15		T3	6
valid_sources[0x55]	373395	1			T1	489		T2	11		T3	3
valid_sources[0x56]	386947	1			T1	785		T2	21		T3	1
valid_sources[0x57]	378215	1			T1	806		T2	16		T3	7
valid_sources[0x58]	372533	1			T1	413		T2	18		T3	5
valid_sources[0x59]	399515	1			T1	912		T2	16		T3	7
valid_sources[0x5a]	404397	1			T1	590		T2	14		T3	6
valid_sources[0x5b]	388331	1			T1	776		T2	18		T4	6
valid_sources[0x5c]	411341	1			T1	1697		T2	12		T3	3
valid_sources[0x5d]	461812	1			T1	1060		T2	8		T4	4
valid_sources[0x5e]	387442	1			T1	772		T2	6		T3	14
valid_sources[0x5f]	372851	1			T1	568		T2	6		T4	10
valid_sources[0x60]	410298	1			T1	564		T2	10		T3	12
valid_sources[0x61]	507600	1			T1	541		T2	9		T3	20
valid_sources[0x62]	380112	1			T1	748		T2	11		T3	10
valid_sources[0x63]	394228	1			T1	422		T2	8		T3	9
valid_sources[0x64]	372100	1			T1	590		T2	19		T3	12
valid_sources[0x65]	373967	1			T1	732		T2	17		T3	2
valid_sources[0x66]	388992	1			T1	1012		T2	10		T3	7
valid_sources[0x67]	399677	1			T1	1023		T2	9		T3	11
valid_sources[0x68]	373605	1			T1	1403		T2	5		T3	17
valid_sources[0x69]	393199	1			T1	685		T2	7		T3	8
valid_sources[0x6a]	389522	1			T1	356		T2	14		T3	7
valid_sources[0x6b]	401687	1			T1	683		T2	7		T3	3
valid_sources[0x6c]	381954	1			T1	553		T2	5		T3	1
valid_sources[0x6d]	382459	1			T1	651		T2	11		T3	9
valid_sources[0x6e]	389015	1			T1	799		T2	9		T3	24
valid_sources[0x6f]	372609	1			T1	661		T2	7		T3	13
valid_sources[0x70]	379602	1			T1	824		T2	17		T3	1
valid_sources[0x71]	395728	1			T1	537		T2	11		T3	6
valid_sources[0x72]	372701	1			T1	555		T2	8		T3	2
valid_sources[0x73]	382556	1			T1	348		T2	13		T4	9
valid_sources[0x74]	382798	1			T1	302		T2	6		T3	2
valid_sources[0x75]	425365	1			T1	657		T2	15		T3	7
valid_sources[0x76]	383498	1			T1	878		T2	9		T3	11
valid_sources[0x77]	382253	1			T1	1186		T2	10		T3	11
valid_sources[0x78]	403726	1			T1	395		T2	9		T3	1
valid_sources[0x79]	373749	1			T1	1099		T2	17		T3	5
valid_sources[0x7a]	380968	1			T1	901		T2	11		T3	9
valid_sources[0x7b]	407971	1			T1	1001		T2	12		T3	3
valid_sources[0x7c]	389001	1			T1	1268		T2	17		T3	2
valid_sources[0x7d]	380639	1			T1	1373		T2	13		T3	7
valid_sources[0x7e]	391545	1			T1	1167		T2	3		T3	12
valid_sources[0x7f]	387225	1			T1	809		T2	11		T3	3
valid_sources[0x80]	393305	1			T1	1025		T2	11		T4	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18637925

1

T1

60018

T2

1

T3

6

values[0x0]

all_enables

biggest_size

4702896

1

T1

118

T2

10

T3

3

values[0x1]

all_enables

biggest_size

4644225

1

T1

64

T2

10

T3

1