Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14738718	0	0
ctrl_rd_A	2147483647	169762	0	0
intr_enable_rd_A	2147483647	150130	0	0
ovrd_rd_A	2147483647	168522	0	0
timeout_ctrl_rd_A	2147483647	170716	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14738718	0	0
T3	224718	71618	0	0
T4	479741	0	0	0
T5	96009	0	0	0
T6	145193	0	0	0
T7	83253	0	0	0
T8	194569	0	0	0
T9	414988	0	0	0
T10	158254	0	0	0
T19	889186	0	0	0
T23	0	97128	0	0
T24	0	273348	0	0
T25	248440	0	0	0
T33	0	78603	0	0
T34	0	164123	0	0
T35	0	259656	0	0
T36	0	287028	0	0
T37	0	317945	0	0
T38	0	201380	0	0
T39	0	70316	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	169762	0	0
T3	224718	2810	0	0
T4	479741	0	0	0
T5	96009	0	0	0
T6	145193	0	0	0
T7	83253	0	0	0
T8	194569	0	0	0
T9	414988	0	0	0
T10	158254	0	0	0
T19	889186	0	0	0
T25	248440	0	0	0
T33	0	4001	0	0
T47	0	9352	0	0
T110	0	9009	0	0
T111	0	6898	0	0
T112	0	2095	0	0
T113	0	10589	0	0
T114	0	3792	0	0
T115	0	8341	0	0
T116	0	5179	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	150130	0	0
T3	224718	2313	0	0
T4	479741	0	0	0
T5	96009	0	0	0
T6	145193	0	0	0
T7	83253	0	0	0
T8	194569	0	0	0
T9	414988	0	0	0
T10	158254	0	0	0
T19	889186	0	0	0
T25	248440	0	0	0
T33	0	3524	0	0
T45	0	21	0	0
T47	0	8121	0	0
T110	0	7999	0	0
T111	0	5900	0	0
T112	0	1597	0	0
T113	0	8519	0	0
T114	0	3294	0	0
T117	0	10	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	168522	0	0
T3	224718	2853	0	0
T4	479741	0	0	0
T5	96009	0	0	0
T6	145193	0	0	0
T7	83253	0	0	0
T8	194569	0	0	0
T9	414988	0	0	0
T10	158254	0	0	0
T19	889186	0	0	0
T25	248440	0	0	0
T33	0	3872	0	0
T47	0	9026	0	0
T110	0	8928	0	0
T111	0	6798	0	0
T112	0	1952	0	0
T113	0	10141	0	0
T114	0	3778	0	0
T115	0	8734	0	0
T116	0	5141	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	170716	0	0
T3	224718	2649	0	0
T4	479741	0	0	0
T5	96009	0	0	0
T6	145193	0	0	0
T7	83253	0	0	0
T8	194569	0	0	0
T9	414988	0	0	0
T10	158254	0	0	0
T19	889186	0	0	0
T25	248440	0	0	0
T33	0	3932	0	0
T47	0	9186	0	0
T110	0	9132	0	0
T111	0	7034	0	0
T112	0	1892	0	0
T113	0	10035	0	0
T114	0	4213	0	0
T115	0	8417	0	0
T116	0	5356	0	0