Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	70721722	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

26767192

1

T1

414

T2

52

T3

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	87773506	1			T1	1541		T2	404		T3	1543
values[0x0]	4590794	1			T1	192		T2	68		T3	21
values[0x1]	5124614	1			T1	189		T2	71		T3	28

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	48777296	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

48711618

1

T1

791

T2

198

T3

535

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	338224	1			T1	3		T2	3		T3	2
valid_sources[0x01]	367267	1			T1	7		T2	5		T3	14
valid_sources[0x02]	372668	1			T1	4		T3	7		T4	51
valid_sources[0x03]	441273	1			T1	3		T2	1		T3	6
valid_sources[0x04]	449098	1			T1	4		T2	8		T4	45
valid_sources[0x05]	354869	1			T1	5		T2	2		T4	44
valid_sources[0x06]	357084	1			T1	8		T2	17		T4	46
valid_sources[0x07]	495634	1			T1	12		T2	3		T3	17
valid_sources[0x08]	386570	1			T1	5		T2	2		T3	6
valid_sources[0x09]	581600	1			T1	8		T4	53		T6	68
valid_sources[0x0a]	381953	1			T1	9		T2	6		T3	3
valid_sources[0x0b]	392980	1			T1	6		T3	1		T4	54
valid_sources[0x0c]	340050	1			T1	4		T2	2		T3	21
valid_sources[0x0d]	357049	1			T1	12		T3	12		T4	44
valid_sources[0x0e]	378919	1			T1	8		T3	6		T4	44
valid_sources[0x0f]	340882	1			T1	7		T3	13		T4	49
valid_sources[0x10]	427136	1			T1	17		T2	14		T3	2
valid_sources[0x11]	358630	1			T1	5		T3	22		T4	36
valid_sources[0x12]	399434	1			T1	7		T2	4		T3	42
valid_sources[0x13]	360367	1			T1	6		T4	51		T6	72
valid_sources[0x14]	388058	1			T1	5		T3	1		T4	42
valid_sources[0x15]	352824	1			T1	9		T4	49		T6	103
valid_sources[0x16]	357751	1			T1	6		T4	46		T6	88
valid_sources[0x17]	365359	1			T1	6		T2	9		T3	1
valid_sources[0x18]	419550	1			T1	7		T2	1		T3	17
valid_sources[0x19]	368317	1			T1	5		T2	5		T3	1
valid_sources[0x1a]	350922	1			T1	6		T3	13		T4	50
valid_sources[0x1b]	377534	1			T1	8		T4	43		T6	61
valid_sources[0x1c]	438229	1			T1	3		T3	8		T4	59
valid_sources[0x1d]	334650	1			T1	10		T3	21		T4	51
valid_sources[0x1e]	384685	1			T1	7		T2	14		T3	4
valid_sources[0x1f]	400949	1			T1	8		T3	1		T4	33
valid_sources[0x20]	355808	1			T1	8		T3	10		T4	56
valid_sources[0x21]	454497	1			T1	7		T4	61		T6	85
valid_sources[0x22]	355209	1			T1	9		T2	8		T3	3
valid_sources[0x23]	339227	1			T1	12		T2	2		T4	47
valid_sources[0x24]	350811	1			T1	3		T3	6		T4	44
valid_sources[0x25]	402894	1			T1	5		T2	9		T3	7
valid_sources[0x26]	346124	1			T1	10		T2	4		T3	2
valid_sources[0x27]	351426	1			T1	7		T4	54		T6	106
valid_sources[0x28]	346174	1			T1	6		T2	2		T4	50
valid_sources[0x29]	359244	1			T1	6		T2	10		T4	44
valid_sources[0x2a]	367087	1			T1	7		T2	1		T3	15
valid_sources[0x2b]	430561	1			T1	3		T3	2		T4	45
valid_sources[0x2c]	355637	1			T1	2		T4	51		T6	92
valid_sources[0x2d]	387211	1			T1	18		T3	5		T4	51
valid_sources[0x2e]	425461	1			T1	1		T3	31		T4	51
valid_sources[0x2f]	357816	1			T1	13		T2	2		T4	48
valid_sources[0x30]	361882	1			T1	7		T2	1		T3	15
valid_sources[0x31]	395896	1			T1	8		T4	44		T6	51
valid_sources[0x32]	361098	1			T1	3		T2	5		T4	47
valid_sources[0x33]	375781	1			T1	10		T2	14		T3	7
valid_sources[0x34]	590828	1			T1	9		T2	1		T3	11
valid_sources[0x35]	349059	1			T1	3		T2	4		T3	2
valid_sources[0x36]	350062	1			T1	5		T3	15		T4	36
valid_sources[0x37]	370132	1			T1	5		T2	12		T3	4
valid_sources[0x38]	550981	1			T1	8		T4	50		T6	91
valid_sources[0x39]	342780	1			T1	2		T3	2		T4	64
valid_sources[0x3a]	388781	1			T1	4		T2	4		T3	2
valid_sources[0x3b]	407801	1			T1	8		T3	9		T4	50
valid_sources[0x3c]	451463	1			T1	8		T2	7		T4	72
valid_sources[0x3d]	336805	1			T1	13		T3	17		T4	53
valid_sources[0x3e]	366354	1			T1	2		T4	54		T6	102
valid_sources[0x3f]	362995	1			T1	7		T2	2		T4	62
valid_sources[0x40]	367493	1			T1	7		T4	47		T6	92
valid_sources[0x41]	346956	1			T1	4		T2	1		T4	46
valid_sources[0x42]	355634	1			T1	6		T2	6		T3	5
valid_sources[0x43]	369382	1			T1	4		T2	6		T3	8
valid_sources[0x44]	434596	1			T1	6		T4	42		T6	83
valid_sources[0x45]	385563	1			T1	9		T2	3		T3	7
valid_sources[0x46]	367451	1			T1	9		T3	1		T4	46
valid_sources[0x47]	346793	1			T1	6		T2	8		T3	5
valid_sources[0x48]	348344	1			T1	15		T2	7		T3	14
valid_sources[0x49]	339548	1			T1	8		T3	10		T4	53
valid_sources[0x4a]	336845	1			T1	10		T4	56		T6	60
valid_sources[0x4b]	612856	1			T1	3		T4	50		T5	1157
valid_sources[0x4c]	363997	1			T1	6		T3	30		T4	36
valid_sources[0x4d]	384085	1			T1	5		T2	3		T3	1
valid_sources[0x4e]	365006	1			T1	13		T4	58		T6	101
valid_sources[0x4f]	437046	1			T1	12		T3	5		T4	57
valid_sources[0x50]	445707	1			T1	9		T2	3		T3	10
valid_sources[0x51]	441104	1			T1	5		T2	1		T3	8
valid_sources[0x52]	411629	1			T3	14		T4	58		T6	96
valid_sources[0x53]	344697	1			T1	4		T3	1		T4	52
valid_sources[0x54]	430631	1			T1	4		T3	25		T4	53
valid_sources[0x55]	337131	1			T1	6		T4	40		T6	62
valid_sources[0x56]	538503	1			T1	12		T2	1		T3	14
valid_sources[0x57]	351889	1			T1	7		T2	1		T4	55
valid_sources[0x58]	395623	1			T1	4		T2	17		T4	55
valid_sources[0x59]	370231	1			T1	8		T4	49		T6	66
valid_sources[0x5a]	381028	1			T1	5		T2	1		T4	50
valid_sources[0x5b]	343166	1			T1	8		T4	43		T6	104
valid_sources[0x5c]	343847	1			T1	14		T2	2		T3	12
valid_sources[0x5d]	376351	1			T1	9		T3	3		T4	41
valid_sources[0x5e]	354271	1			T1	5		T4	55		T6	76
valid_sources[0x5f]	325443	1			T1	10		T2	1		T4	63
valid_sources[0x60]	395894	1			T1	13		T3	6		T4	50
valid_sources[0x61]	405816	1			T1	16		T3	14		T4	50
valid_sources[0x62]	384679	1			T1	12		T2	8		T3	7
valid_sources[0x63]	483687	1			T1	5		T3	30		T4	61
valid_sources[0x64]	375600	1			T1	5		T3	10		T4	61
valid_sources[0x65]	372400	1			T1	3		T3	2		T4	46
valid_sources[0x66]	352960	1			T1	1		T3	9		T4	56
valid_sources[0x67]	394120	1			T1	6		T4	57		T5	222
valid_sources[0x68]	371462	1			T1	9		T2	3		T3	5
valid_sources[0x69]	369758	1			T1	12		T3	13		T4	41
valid_sources[0x6a]	374428	1			T1	9		T2	1		T3	10
valid_sources[0x6b]	649919	1			T1	10		T2	10		T3	2
valid_sources[0x6c]	363608	1			T1	10		T2	3		T3	11
valid_sources[0x6d]	338393	1			T1	9		T3	14		T4	54
valid_sources[0x6e]	385232	1			T1	7		T3	5		T4	40
valid_sources[0x6f]	433385	1			T1	5		T3	7		T4	47
valid_sources[0x70]	366975	1			T1	10		T2	1		T3	6
valid_sources[0x71]	356970	1			T1	8		T4	49		T6	91
valid_sources[0x72]	364614	1			T1	7		T4	46		T6	53
valid_sources[0x73]	377555	1			T1	2		T2	6		T4	61
valid_sources[0x74]	356690	1			T1	4		T2	8		T3	13
valid_sources[0x75]	351987	1			T1	5		T4	44		T6	95
valid_sources[0x76]	352165	1			T1	6		T2	11		T4	48
valid_sources[0x77]	363442	1			T1	8		T3	14		T4	70
valid_sources[0x78]	358025	1			T1	14		T2	18		T4	45
valid_sources[0x79]	374541	1			T1	7		T2	1		T4	45
valid_sources[0x7a]	341126	1			T1	9		T2	1		T4	53
valid_sources[0x7b]	494598	1			T1	6		T2	2		T3	3
valid_sources[0x7c]	386083	1			T1	10		T4	47		T6	63
valid_sources[0x7d]	449392	1			T1	7		T2	3		T3	1
valid_sources[0x7e]	356278	1			T1	1		T3	6		T4	63
valid_sources[0x7f]	392476	1			T1	5		T2	4		T4	47
valid_sources[0x80]	367862	1			T1	3		T2	3		T3	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18129774

1

T1

312

T2

8

T3

7

values[0x0]

all_enables

biggest_size

4345732

1

T1

64

T2

30

T3

8

values[0x1]

all_enables

biggest_size

4291686

1

T1

38

T2

14

T3

3