Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14277996	0	0
ctrl_rd_A	2147483647	276536	0	0
intr_enable_rd_A	2147483647	246841	0	0
ovrd_rd_A	2147483647	277075	0	0
timeout_ctrl_rd_A	2147483647	276405	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14277996	0	0
T11	428444	0	0	0
T12	477129	192658	0	0
T14	220523	0	0	0
T22	0	184321	0	0
T23	0	83193	0	0
T24	190273	47893	0	0
T25	0	48362	0	0
T28	259536	0	0	0
T35	0	173637	0	0
T36	0	170281	0	0
T37	0	97205	0	0
T38	0	102907	0	0
T39	0	65126	0	0
T40	204550	0	0	0
T41	305519	0	0	0
T42	153111	0	0	0
T43	291798	0	0	0
T44	41957	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	276536	0	0
T11	428444	0	0	0
T14	220523	0	0	0
T23	0	9544	0	0
T24	190273	5162	0	0
T28	259536	0	0	0
T36	0	7794	0	0
T38	0	2601	0	0
T39	0	7237	0	0
T40	204550	0	0	0
T41	305519	0	0	0
T42	153111	0	0	0
T43	291798	0	0	0
T44	41957	0	0	0
T56	0	17854	0	0
T117	0	6913	0	0
T118	0	6942	0	0
T119	0	6682	0	0
T120	0	7613	0	0
T121	656121	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	246841	0	0
T11	428444	0	0	0
T14	220523	0	0	0
T23	0	8562	0	0
T24	190273	4442	0	0
T28	259536	0	0	0
T36	0	6649	0	0
T38	0	2271	0	0
T39	0	6513	0	0
T40	204550	0	0	0
T41	305519	0	0	0
T42	153111	0	0	0
T43	291798	0	0	0
T44	41957	0	0	0
T99	0	22	0	0
T117	0	6081	0	0
T118	0	6183	0	0
T119	0	6226	0	0
T120	0	7216	0	0
T121	656121	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	277075	0	0
T11	428444	0	0	0
T14	220523	0	0	0
T23	0	9638	0	0
T24	190273	5080	0	0
T28	259536	0	0	0
T36	0	7744	0	0
T38	0	2766	0	0
T39	0	7060	0	0
T40	204550	0	0	0
T41	305519	0	0	0
T42	153111	0	0	0
T43	291798	0	0	0
T44	41957	0	0	0
T56	0	17663	0	0
T117	0	6993	0	0
T118	0	6938	0	0
T119	0	6677	0	0
T120	0	8775	0	0
T121	656121	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	276405	0	0
T11	428444	0	0	0
T14	220523	0	0	0
T23	0	9337	0	0
T24	190273	5044	0	0
T28	259536	0	0	0
T36	0	7729	0	0
T38	0	2634	0	0
T39	0	7386	0	0
T40	204550	0	0	0
T41	305519	0	0	0
T42	153111	0	0	0
T43	291798	0	0	0
T44	41957	0	0	0
T56	0	17525	0	0
T117	0	6730	0	0
T118	0	6988	0	0
T119	0	6792	0	0
T120	0	8362	0	0
T121	656121	0	0	0