Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	15657108	0	0
ctrl_rd_A	2147483647	260080	0	0
intr_enable_rd_A	2147483647	231810	0	0
ovrd_rd_A	2147483647	259390	0	0
timeout_ctrl_rd_A	2147483647	258393	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15657108	0	0
T5	473498	199925	0	0
T6	736711	0	0	0
T7	325500	126708	0	0
T8	142551	0	0	0
T9	992018	0	0	0
T10	536155	0	0	0
T11	62683	0	0	0
T13	0	103394	0	0
T14	0	44835	0	0
T15	0	86419	0	0
T17	1138	0	0	0
T23	0	175662	0	0
T24	0	527095	0	0
T25	0	95100	0	0
T26	0	231436	0	0
T27	0	164123	0	0
T28	203171	0	0	0
T29	839468	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	260080	0	0
T12	103654	0	0	0
T13	426997	11108	0	0
T15	0	9009	0	0
T18	1332	0	0	0
T19	794	0	0	0
T23	692411	19779	0	0
T31	409740	0	0	0
T44	0	5558	0	0
T91	0	17453	0	0
T92	0	5968	0	0
T93	0	7330	0	0
T94	0	5170	0	0
T95	0	3672	0	0
T96	0	5441	0	0
T97	825918	0	0	0
T98	419526	0	0	0
T99	142524	0	0	0
T100	328776	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	231810	0	0
T12	103654	37	0	0
T13	426997	9803	0	0
T15	0	8801	0	0
T18	1332	0	0	0
T19	794	0	0	0
T23	692411	16835	0	0
T31	409740	0	0	0
T44	0	5087	0	0
T91	0	14789	0	0
T92	0	5340	0	0
T93	0	6421	0	0
T94	0	4140	0	0
T97	825918	0	0	0
T98	419526	0	0	0
T99	142524	0	0	0
T100	328776	0	0	0
T101	0	8	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	259390	0	0
T12	103654	0	0	0
T13	426997	11221	0	0
T15	0	9199	0	0
T18	1332	0	0	0
T19	794	0	0	0
T23	692411	19866	0	0
T31	409740	0	0	0
T44	0	5430	0	0
T91	0	17017	0	0
T92	0	6126	0	0
T93	0	7116	0	0
T94	0	4843	0	0
T95	0	3495	0	0
T96	0	5510	0	0
T97	825918	0	0	0
T98	419526	0	0	0
T99	142524	0	0	0
T100	328776	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	258393	0	0
T12	103654	0	0	0
T13	426997	11168	0	0
T15	0	9590	0	0
T18	1332	0	0	0
T19	794	0	0	0
T23	692411	18865	0	0
T31	409740	0	0	0
T44	0	5214	0	0
T91	0	16833	0	0
T92	0	5946	0	0
T93	0	7461	0	0
T94	0	4812	0	0
T95	0	3785	0	0
T96	0	5328	0	0
T97	825918	0	0	0
T98	419526	0	0	0
T99	142524	0	0	0
T100	328776	0	0	0