Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	71395317	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

26636413

1

T1

165

T2

201

T3

96

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	88498389	1			T1	31290		T2	164248		T3	114486
values[0x0]	4503583	1			T1	131		T2	283		T3	101
values[0x1]	5029758	1			T1	141		T2	279		T3	102

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	49358757	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

48672973

1

T1

10534

T2

55116

T3

38264

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	371391	1			T2	644		T3	454		T5	23
valid_sources[0x01]	385805	1			T2	583		T3	465		T5	30
valid_sources[0x02]	369595	1			T2	682		T3	515		T5	23
valid_sources[0x03]	349533	1			T2	656		T3	399		T5	19
valid_sources[0x04]	402890	1			T2	650		T3	506		T5	22
valid_sources[0x05]	459408	1			T2	686		T3	442		T5	19
valid_sources[0x06]	376358	1			T2	620		T3	470		T5	27
valid_sources[0x07]	422441	1			T2	651		T3	381		T5	21
valid_sources[0x08]	362201	1			T2	683		T3	433		T5	20
valid_sources[0x09]	348362	1			T2	680		T3	478		T5	17
valid_sources[0x0a]	438562	1			T2	622		T3	412		T5	12
valid_sources[0x0b]	363585	1			T2	664		T3	436		T5	31
valid_sources[0x0c]	417801	1			T2	667		T3	538		T5	18
valid_sources[0x0d]	365349	1			T2	652		T3	506		T5	25
valid_sources[0x0e]	365450	1			T2	614		T3	534		T5	29
valid_sources[0x0f]	447442	1			T2	678		T3	415		T5	23
valid_sources[0x10]	371145	1			T2	618		T3	396		T5	22
valid_sources[0x11]	355286	1			T2	599		T3	400		T5	21
valid_sources[0x12]	357492	1			T2	638		T3	454		T5	18
valid_sources[0x13]	360398	1			T2	643		T3	424		T5	20
valid_sources[0x14]	374380	1			T2	647		T3	453		T5	20
valid_sources[0x15]	374614	1			T2	584		T3	527		T5	14
valid_sources[0x16]	357515	1			T2	681		T3	499		T5	19
valid_sources[0x17]	361003	1			T2	691		T3	491		T5	20
valid_sources[0x18]	414480	1			T2	650		T3	530		T5	26
valid_sources[0x19]	387340	1			T2	701		T3	379		T5	25
valid_sources[0x1a]	389323	1			T2	659		T3	444		T5	16
valid_sources[0x1b]	368754	1			T2	654		T3	412		T5	31
valid_sources[0x1c]	379422	1			T2	641		T3	416		T5	33
valid_sources[0x1d]	392968	1			T2	625		T3	370		T5	26
valid_sources[0x1e]	351911	1			T2	623		T3	414		T5	15
valid_sources[0x1f]	354621	1			T2	630		T3	442		T5	16
valid_sources[0x20]	404590	1			T2	652		T3	350		T5	16
valid_sources[0x21]	341348	1			T2	636		T3	405		T5	23
valid_sources[0x22]	359285	1			T2	628		T3	468		T5	15
valid_sources[0x23]	373522	1			T2	678		T3	526		T5	17
valid_sources[0x24]	344967	1			T2	628		T3	415		T5	16
valid_sources[0x25]	391577	1			T2	636		T3	452		T5	31
valid_sources[0x26]	364217	1			T2	662		T3	523		T5	21
valid_sources[0x27]	355464	1			T2	671		T3	390		T5	18
valid_sources[0x28]	350174	1			T2	649		T3	442		T5	22
valid_sources[0x29]	374491	1			T2	637		T3	445		T5	19
valid_sources[0x2a]	489015	1			T2	670		T3	447		T5	19
valid_sources[0x2b]	363551	1			T2	624		T3	399		T5	19
valid_sources[0x2c]	345089	1			T2	626		T3	362		T5	24
valid_sources[0x2d]	350839	1			T2	697		T3	565		T5	17
valid_sources[0x2e]	448818	1			T2	614		T3	379		T5	21
valid_sources[0x2f]	395162	1			T2	670		T3	479		T5	28
valid_sources[0x30]	360765	1			T2	631		T3	511		T5	28
valid_sources[0x31]	381792	1			T2	668		T3	455		T5	19
valid_sources[0x32]	343247	1			T2	655		T3	406		T5	23
valid_sources[0x33]	364877	1			T2	627		T3	433		T5	34
valid_sources[0x34]	429526	1			T2	674		T3	344		T5	14
valid_sources[0x35]	406636	1			T2	616		T3	395		T5	25
valid_sources[0x36]	376894	1			T2	650		T3	401		T5	32
valid_sources[0x37]	371763	1			T2	638		T3	396		T5	29
valid_sources[0x38]	355839	1			T2	667		T3	490		T5	37
valid_sources[0x39]	456777	1			T2	635		T3	525		T5	20
valid_sources[0x3a]	390244	1			T2	617		T3	411		T5	22
valid_sources[0x3b]	379414	1			T2	662		T3	449		T5	12
valid_sources[0x3c]	372671	1			T2	644		T3	467		T5	20
valid_sources[0x3d]	352444	1			T2	626		T3	447		T5	24
valid_sources[0x3e]	349112	1			T2	670		T3	421		T5	20
valid_sources[0x3f]	439005	1			T2	653		T3	427		T5	25
valid_sources[0x40]	342050	1			T2	666		T3	459		T5	35
valid_sources[0x41]	379067	1			T2	667		T3	497		T5	14
valid_sources[0x42]	476996	1			T1	11652		T2	660		T3	425
valid_sources[0x43]	360713	1			T2	610		T3	451		T5	16
valid_sources[0x44]	352690	1			T2	669		T3	490		T5	26
valid_sources[0x45]	402671	1			T2	622		T3	482		T5	18
valid_sources[0x46]	356263	1			T2	622		T3	487		T5	23
valid_sources[0x47]	429317	1			T1	19910		T2	659		T3	371
valid_sources[0x48]	372032	1			T2	622		T3	536		T5	25
valid_sources[0x49]	472769	1			T2	689		T3	428		T5	33
valid_sources[0x4a]	383404	1			T2	640		T3	361		T5	25
valid_sources[0x4b]	358604	1			T2	622		T3	403		T5	27
valid_sources[0x4c]	370707	1			T2	563		T3	390		T5	28
valid_sources[0x4d]	364936	1			T2	682		T3	483		T5	29
valid_sources[0x4e]	479449	1			T2	681		T3	486		T5	11
valid_sources[0x4f]	373659	1			T2	633		T3	410		T5	21
valid_sources[0x50]	362032	1			T2	720		T3	371		T5	18
valid_sources[0x51]	445010	1			T2	639		T3	457		T5	31
valid_sources[0x52]	364503	1			T2	624		T3	455		T5	16
valid_sources[0x53]	353523	1			T2	653		T3	468		T5	14
valid_sources[0x54]	356203	1			T2	626		T3	420		T5	23
valid_sources[0x55]	354048	1			T2	644		T3	431		T5	29
valid_sources[0x56]	367321	1			T2	670		T3	411		T5	24
valid_sources[0x57]	358196	1			T2	615		T3	457		T5	27
valid_sources[0x58]	393137	1			T2	685		T3	510		T5	27
valid_sources[0x59]	390245	1			T2	664		T3	448		T5	24
valid_sources[0x5a]	411165	1			T2	603		T3	378		T5	27
valid_sources[0x5b]	434246	1			T2	624		T3	423		T5	28
valid_sources[0x5c]	345182	1			T2	636		T3	445		T5	20
valid_sources[0x5d]	346689	1			T2	623		T3	439		T5	19
valid_sources[0x5e]	350775	1			T2	632		T3	431		T5	30
valid_sources[0x5f]	354992	1			T2	615		T3	477		T5	35
valid_sources[0x60]	350956	1			T2	681		T3	463		T5	23
valid_sources[0x61]	367117	1			T2	641		T3	466		T5	22
valid_sources[0x62]	373501	1			T2	681		T3	340		T5	25
valid_sources[0x63]	345369	1			T2	631		T3	454		T5	21
valid_sources[0x64]	354461	1			T2	635		T3	428		T5	21
valid_sources[0x65]	339910	1			T2	619		T3	345		T5	32
valid_sources[0x66]	390969	1			T2	676		T3	424		T5	20
valid_sources[0x67]	405305	1			T2	683		T3	459		T5	16
valid_sources[0x68]	362546	1			T2	634		T3	434		T5	40
valid_sources[0x69]	364700	1			T2	620		T3	379		T5	30
valid_sources[0x6a]	465772	1			T2	645		T3	496		T5	20
valid_sources[0x6b]	393064	1			T2	618		T3	450		T5	29
valid_sources[0x6c]	359764	1			T2	623		T3	438		T5	21
valid_sources[0x6d]	370463	1			T2	637		T3	410		T5	16
valid_sources[0x6e]	391182	1			T2	659		T3	510		T5	21
valid_sources[0x6f]	369266	1			T2	628		T3	498		T5	25
valid_sources[0x70]	377708	1			T2	633		T3	514		T5	23
valid_sources[0x71]	485431	1			T2	652		T3	429		T5	18
valid_sources[0x72]	388605	1			T2	668		T3	420		T5	17
valid_sources[0x73]	450730	1			T2	645		T3	400		T5	23
valid_sources[0x74]	467147	1			T2	600		T3	451		T5	36
valid_sources[0x75]	449496	1			T2	671		T3	427		T5	22
valid_sources[0x76]	389839	1			T2	637		T3	408		T5	23
valid_sources[0x77]	395535	1			T2	624		T3	386		T5	31
valid_sources[0x78]	352984	1			T2	615		T3	374		T5	25
valid_sources[0x79]	350245	1			T2	676		T3	440		T5	18
valid_sources[0x7a]	365859	1			T2	643		T3	412		T5	22
valid_sources[0x7b]	396440	1			T2	635		T3	430		T5	21
valid_sources[0x7c]	563892	1			T2	622		T3	567		T5	17
valid_sources[0x7d]	395674	1			T2	617		T3	444		T5	27
valid_sources[0x7e]	349690	1			T2	667		T3	479		T5	30
valid_sources[0x7f]	428360	1			T2	662		T3	562		T5	29
valid_sources[0x80]	353566	1			T2	626		T3	455		T5	25

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18216441

1

T1

75

T2

45

T3

33

values[0x0]

all_enables

biggest_size

4239622

1

T1

55

T2

102

T3

45

values[0x1]

all_enables

biggest_size

4180350

1

T1

35

T2

54

T3

18