Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14055687	0	0
ctrl_rd_A	2147483647	180483	0	0
intr_enable_rd_A	2147483647	160105	0	0
ovrd_rd_A	2147483647	179442	0	0
timeout_ctrl_rd_A	2147483647	179649	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14055687	0	0
T11	289670	76673	0	0
T12	634884	196773	0	0
T14	0	223213	0	0
T18	311709	134507	0	0
T23	519053	0	0	0
T34	0	55269	0	0
T35	0	213448	0	0
T36	0	149132	0	0
T37	0	133920	0	0
T38	0	207301	0	0
T39	0	136494	0	0
T40	305550	0	0	0
T41	171646	0	0	0
T42	856268	0	0	0
T43	899764	0	0	0
T44	602327	0	0	0
T45	978774	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	180483	0	0
T11	289670	3436	0	0
T12	634884	0	0	0
T18	311709	0	0	0
T23	519053	0	0	0
T34	0	2832	0	0
T38	0	10528	0	0
T40	305550	0	0	0
T41	171646	0	0	0
T42	856268	0	0	0
T43	899764	0	0	0
T44	602327	0	0	0
T45	978774	0	0	0
T119	0	18123	0	0
T120	0	5024	0	0
T121	0	5285	0	0
T122	0	5378	0	0
T123	0	4901	0	0
T124	0	8457	0	0
T125	0	5346	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	160105	0	0
T11	289670	3133	0	0
T12	634884	0	0	0
T18	311709	0	0	0
T23	519053	0	0	0
T34	0	2521	0	0
T38	0	9265	0	0
T40	305550	0	0	0
T41	171646	0	0	0
T42	856268	0	0	0
T43	899764	0	0	0
T44	602327	0	0	0
T45	978774	0	0	0
T119	0	15842	0	0
T120	0	4369	0	0
T121	0	4705	0	0
T122	0	4817	0	0
T123	0	4257	0	0
T124	0	8009	0	0
T125	0	5037	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	179442	0	0
T11	289670	3439	0	0
T12	634884	0	0	0
T18	311709	0	0	0
T23	519053	0	0	0
T34	0	2794	0	0
T38	0	10346	0	0
T40	305550	0	0	0
T41	171646	0	0	0
T42	856268	0	0	0
T43	899764	0	0	0
T44	602327	0	0	0
T45	978774	0	0	0
T119	0	17625	0	0
T120	0	5127	0	0
T121	0	5187	0	0
T122	0	5460	0	0
T123	0	4695	0	0
T124	0	9254	0	0
T125	0	5440	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	179649	0	0
T11	289670	3261	0	0
T12	634884	0	0	0
T18	311709	0	0	0
T23	519053	0	0	0
T34	0	2682	0	0
T38	0	10539	0	0
T40	305550	0	0	0
T41	171646	0	0	0
T42	856268	0	0	0
T43	899764	0	0	0
T44	602327	0	0	0
T45	978774	0	0	0
T119	0	18164	0	0
T120	0	5224	0	0
T121	0	5379	0	0
T122	0	5549	0	0
T123	0	4994	0	0
T124	0	8976	0	0
T125	0	5235	0	0