Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	15425295	0	0
ctrl_rd_A	2147483647	280202	0	0
intr_enable_rd_A	2147483647	249170	0	0
ovrd_rd_A	2147483647	280188	0	0
timeout_ctrl_rd_A	2147483647	280305	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15425295	0	0
T4	271656	112586	0	0
T5	674883	0	0	0
T6	146181	0	0	0
T7	723503	205582	0	0
T8	150472	0	0	0
T9	23546	0	0	0
T10	270882	107959	0	0
T11	101333	0	0	0
T13	0	44344	0	0
T14	0	60460	0	0
T20	0	195373	0	0
T28	0	193500	0	0
T29	0	218657	0	0
T30	0	197731	0	0
T31	0	317983	0	0
T32	203486	0	0	0
T33	165706	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	280202	0	0
T7	723503	15349	0	0
T8	150472	0	0	0
T9	23546	0	0	0
T10	270882	0	0	0
T11	101333	0	0	0
T14	219815	0	0	0
T25	5559	0	0	0
T32	203486	0	0	0
T33	165706	0	0	0
T34	129554	0	0	0
T50	0	28150	0	0
T107	0	10068	0	0
T108	0	24984	0	0
T109	0	2434	0	0
T110	0	11399	0	0
T111	0	7541	0	0
T112	0	4474	0	0
T113	0	6511	0	0
T114	0	2626	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	249170	0	0
T7	723503	13457	0	0
T8	150472	0	0	0
T9	23546	0	0	0
T10	270882	0	0	0
T11	101333	0	0	0
T14	219815	0	0	0
T15	0	18	0	0
T25	5559	0	0	0
T32	203486	0	0	0
T33	165706	0	0	0
T34	129554	0	0	0
T50	0	24996	0	0
T107	0	8657	0	0
T108	0	21919	0	0
T109	0	2094	0	0
T110	0	10551	0	0
T111	0	6895	0	0
T112	0	4415	0	0
T115	0	12	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	280188	0	0
T7	723503	15094	0	0
T8	150472	0	0	0
T9	23546	0	0	0
T10	270882	0	0	0
T11	101333	0	0	0
T14	219815	0	0	0
T25	5559	0	0	0
T32	203486	0	0	0
T33	165706	0	0	0
T34	129554	0	0	0
T50	0	28057	0	0
T107	0	9840	0	0
T108	0	25387	0	0
T109	0	2238	0	0
T110	0	12676	0	0
T111	0	8194	0	0
T112	0	4922	0	0
T113	0	6826	0	0
T114	0	2846	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	280305	0	0
T7	723503	14654	0	0
T8	150472	0	0	0
T9	23546	0	0	0
T10	270882	0	0	0
T11	101333	0	0	0
T14	219815	0	0	0
T25	5559	0	0	0
T32	203486	0	0	0
T33	165706	0	0	0
T34	129554	0	0	0
T50	0	28605	0	0
T107	0	9830	0	0
T108	0	24944	0	0
T109	0	2309	0	0
T110	0	11858	0	0
T111	0	8166	0	0
T112	0	4734	0	0
T113	0	6753	0	0
T114	0	2621	0	0