Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	74489660	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

28767485

1

T1

5

T2

193

T3

192

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	93453258	1			T1	806		T2	3135		T3	2327
values[0x0]	4634801	1			T1	4		T2	183		T3	42
values[0x1]	5169086	1			T1	6		T2	171		T3	47

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51596819	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

51660326

1

T1

381

T2

1269

T3

864

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	415506	1			T1	3		T2	25		T3	5
valid_sources[0x01]	370021	1			T1	3		T2	6		T3	9
valid_sources[0x02]	381552	1			T1	4		T2	16		T3	5
valid_sources[0x03]	424760	1			T1	4		T2	15		T3	3
valid_sources[0x04]	387580	1			T1	2		T2	1		T3	9
valid_sources[0x05]	402637	1			T1	5		T2	18		T3	11
valid_sources[0x06]	392090	1			T1	5		T2	20		T3	8
valid_sources[0x07]	411392	1			T1	3		T2	15		T3	9
valid_sources[0x08]	377552	1			T1	4		T2	8		T3	8
valid_sources[0x09]	391483	1			T1	4		T2	19		T3	5
valid_sources[0x0a]	373582	1			T1	2		T2	13		T3	8
valid_sources[0x0b]	440439	1			T1	4		T2	26		T3	16
valid_sources[0x0c]	384029	1			T1	3		T2	13		T3	13
valid_sources[0x0d]	406296	1			T1	3		T2	17		T3	10
valid_sources[0x0e]	399355	1			T1	1		T2	14		T3	10
valid_sources[0x0f]	377997	1			T1	1		T2	5		T3	11
valid_sources[0x10]	385366	1			T1	5		T2	8		T3	10
valid_sources[0x11]	372911	1			T1	4		T2	23		T3	10
valid_sources[0x12]	424720	1			T1	3		T2	9		T3	9
valid_sources[0x13]	374664	1			T1	1		T2	17		T3	8
valid_sources[0x14]	391284	1			T2	25		T3	12		T4	2042
valid_sources[0x15]	452141	1			T1	2		T2	15		T3	9
valid_sources[0x16]	437602	1			T1	2		T2	7		T3	12
valid_sources[0x17]	366547	1			T1	3		T2	17		T3	12
valid_sources[0x18]	396204	1			T1	2		T2	16		T3	8
valid_sources[0x19]	411290	1			T1	4		T2	17		T3	17
valid_sources[0x1a]	385232	1			T1	2		T2	9		T3	15
valid_sources[0x1b]	413820	1			T1	4		T2	17		T3	7
valid_sources[0x1c]	421575	1			T1	6		T2	15		T3	15
valid_sources[0x1d]	398919	1			T1	7		T2	16		T3	8
valid_sources[0x1e]	394394	1			T1	6		T2	26		T3	10
valid_sources[0x1f]	383079	1			T1	5		T2	30		T3	7
valid_sources[0x20]	433595	1			T1	4		T2	13		T3	11
valid_sources[0x21]	384128	1			T1	4		T2	20		T3	3
valid_sources[0x22]	441065	1			T1	4		T2	13		T3	13
valid_sources[0x23]	401837	1			T1	4		T2	26		T3	6
valid_sources[0x24]	386035	1			T1	5		T2	19		T3	8
valid_sources[0x25]	386196	1			T1	4		T2	10		T3	8
valid_sources[0x26]	423527	1			T1	5		T2	6		T3	14
valid_sources[0x27]	406224	1			T1	4		T2	9		T3	11
valid_sources[0x28]	414241	1			T1	7		T2	6		T3	10
valid_sources[0x29]	396875	1			T1	4		T2	11		T3	7
valid_sources[0x2a]	436440	1			T1	4		T2	7		T3	12
valid_sources[0x2b]	393443	1			T1	6		T2	14		T3	9
valid_sources[0x2c]	382031	1			T1	5		T2	13		T3	15
valid_sources[0x2d]	390857	1			T1	2		T2	5		T3	14
valid_sources[0x2e]	372388	1			T1	4		T2	4		T3	17
valid_sources[0x2f]	377305	1			T1	4		T2	11		T3	10
valid_sources[0x30]	395353	1			T1	3		T2	5		T3	12
valid_sources[0x31]	415876	1			T1	3		T2	21		T3	10
valid_sources[0x32]	379333	1			T1	4		T2	6		T3	11
valid_sources[0x33]	400072	1			T1	3		T2	14		T3	19
valid_sources[0x34]	391844	1			T1	6		T2	9		T3	5
valid_sources[0x35]	371335	1			T1	3		T2	10		T3	12
valid_sources[0x36]	394256	1			T1	1		T2	8		T3	6
valid_sources[0x37]	388225	1			T2	22		T3	4		T4	2088
valid_sources[0x38]	378809	1			T1	6		T2	20		T3	12
valid_sources[0x39]	431072	1			T1	3		T2	11		T3	11
valid_sources[0x3a]	383185	1			T1	4		T2	16		T3	5
valid_sources[0x3b]	378762	1			T2	9		T3	10		T4	2039
valid_sources[0x3c]	392319	1			T1	3		T2	27		T3	14
valid_sources[0x3d]	395705	1			T1	2		T2	8		T3	10
valid_sources[0x3e]	385959	1			T1	2		T2	5		T3	11
valid_sources[0x3f]	372907	1			T1	2		T2	12		T3	8
valid_sources[0x40]	386274	1			T2	6		T3	9		T4	2175
valid_sources[0x41]	496050	1			T1	3		T2	17		T3	10
valid_sources[0x42]	386080	1			T1	2		T2	8		T3	6
valid_sources[0x43]	398786	1			T1	6		T2	5		T3	8
valid_sources[0x44]	425885	1			T1	2		T2	23		T3	11
valid_sources[0x45]	401969	1			T1	4		T2	18		T3	11
valid_sources[0x46]	396353	1			T1	3		T2	15		T3	12
valid_sources[0x47]	389219	1			T2	1		T3	10		T4	2042
valid_sources[0x48]	369265	1			T1	4		T2	7		T3	12
valid_sources[0x49]	390669	1			T1	4		T2	14		T3	6
valid_sources[0x4a]	394504	1			T1	1		T2	14		T3	10
valid_sources[0x4b]	416323	1			T1	2		T2	7		T3	7
valid_sources[0x4c]	423476	1			T1	5		T2	5		T3	12
valid_sources[0x4d]	374356	1			T1	2		T2	10		T3	9
valid_sources[0x4e]	451282	1			T1	3		T2	29		T3	11
valid_sources[0x4f]	409366	1			T1	2		T2	9		T3	9
valid_sources[0x50]	457180	1			T1	6		T2	18		T3	12
valid_sources[0x51]	385195	1			T1	3		T2	3		T3	16
valid_sources[0x52]	442637	1			T1	4		T2	9		T3	11
valid_sources[0x53]	402623	1			T2	8		T3	12		T4	2078
valid_sources[0x54]	380489	1			T1	6		T2	6		T3	14
valid_sources[0x55]	370060	1			T1	1		T2	12		T3	9
valid_sources[0x56]	397667	1			T1	3		T2	7		T3	17
valid_sources[0x57]	396401	1			T1	2		T2	11		T3	9
valid_sources[0x58]	408742	1			T1	1		T2	15		T3	10
valid_sources[0x59]	391606	1			T1	1		T2	3		T3	5
valid_sources[0x5a]	385902	1			T2	22		T3	4		T4	2061
valid_sources[0x5b]	410462	1			T1	2		T2	17		T3	2
valid_sources[0x5c]	472446	1			T1	2		T2	17		T3	6
valid_sources[0x5d]	391387	1			T1	5		T2	7		T3	7
valid_sources[0x5e]	387720	1			T1	2		T2	27		T3	8
valid_sources[0x5f]	403006	1			T1	2		T2	36		T3	14
valid_sources[0x60]	389825	1			T1	5		T2	14		T3	6
valid_sources[0x61]	387819	1			T1	6		T2	17		T3	8
valid_sources[0x62]	395053	1			T1	1		T2	12		T3	11
valid_sources[0x63]	408071	1			T1	4		T2	19		T3	7
valid_sources[0x64]	375371	1			T1	3		T2	11		T3	11
valid_sources[0x65]	388216	1			T1	3		T2	23		T3	9
valid_sources[0x66]	395328	1			T1	1		T2	10		T3	8
valid_sources[0x67]	375030	1			T1	1		T2	10		T3	14
valid_sources[0x68]	374472	1			T1	6		T2	18		T3	8
valid_sources[0x69]	373839	1			T1	2		T2	4		T3	7
valid_sources[0x6a]	403300	1			T1	2		T2	8		T3	8
valid_sources[0x6b]	379015	1			T1	3		T2	10		T3	13
valid_sources[0x6c]	386197	1			T1	1		T2	9		T3	2
valid_sources[0x6d]	395744	1			T1	1		T2	9		T3	3
valid_sources[0x6e]	424472	1			T1	3		T2	15		T3	8
valid_sources[0x6f]	393610	1			T1	2		T2	2		T3	8
valid_sources[0x70]	378606	1			T1	4		T2	8		T3	6
valid_sources[0x71]	395043	1			T1	2		T2	13		T3	8
valid_sources[0x72]	381071	1			T1	2		T2	16		T3	13
valid_sources[0x73]	367050	1			T1	2		T2	25		T3	8
valid_sources[0x74]	381644	1			T1	2		T2	9		T3	11
valid_sources[0x75]	481834	1			T1	3		T2	7		T3	7
valid_sources[0x76]	444132	1			T1	2		T2	23		T3	14
valid_sources[0x77]	397232	1			T1	5		T2	16		T3	19
valid_sources[0x78]	366418	1			T1	3		T2	20		T3	12
valid_sources[0x79]	397444	1			T1	2		T2	11		T3	9
valid_sources[0x7a]	392885	1			T1	4		T2	21		T3	19
valid_sources[0x7b]	386730	1			T1	2		T2	5		T3	8
valid_sources[0x7c]	422066	1			T1	3		T2	26		T3	15
valid_sources[0x7d]	407666	1			T2	10		T3	11		T4	2003
valid_sources[0x7e]	518067	1			T1	3		T2	19		T3	7
valid_sources[0x7f]	432609	1			T1	5		T2	18		T3	9
valid_sources[0x80]	394801	1			T2	13		T3	8		T4	2121

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

20096236

1

T1

1

T2

70

T3

156

values[0x0]

all_enables

biggest_size

4366041

1

T1

3

T2

78

T3

19

values[0x1]

all_enables

biggest_size

4305208

1

T1

1

T2

45

T3

17