Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14336766	0	0
ctrl_rd_A	2147483647	238386	0	0
intr_enable_rd_A	2147483647	211560	0	0
ovrd_rd_A	2147483647	238298	0	0
timeout_ctrl_rd_A	2147483647	239511	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14336766	0	0
T11	669695	178139	0	0
T13	0	241935	0	0
T18	0	164059	0	0
T25	0	180682	0	0
T31	0	69796	0	0
T32	0	27312	0	0
T33	0	81498	0	0
T34	0	179629	0	0
T35	0	43494	0	0
T36	0	178751	0	0
T37	836207	0	0	0
T38	215014	0	0	0
T39	921892	0	0	0
T40	454427	0	0	0
T41	230415	0	0	0
T42	5066	0	0	0
T43	985648	0	0	0
T44	137502	0	0	0
T45	185293	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	238386	0	0
T14	987338	0	0	0
T16	116171	0	0	0
T19	32900	0	0	0
T31	223484	3321	0	0
T32	0	1127	0	0
T34	0	7453	0	0
T49	0	13489	0	0
T96	0	5415	0	0
T97	0	5363	0	0
T98	0	8490	0	0
T99	0	14443	0	0
T100	0	1052	0	0
T101	0	6220	0	0
T102	234926	0	0	0
T103	78392	0	0	0
T104	489849	0	0	0
T105	1075	0	0	0
T106	684	0	0	0
T107	201033	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	211560	0	0
T14	987338	0	0	0
T16	116171	0	0	0
T19	32900	0	0	0
T31	223484	3138	0	0
T32	0	940	0	0
T34	0	6828	0	0
T96	0	4624	0	0
T97	0	4286	0	0
T98	0	7543	0	0
T99	0	12380	0	0
T100	0	976	0	0
T101	0	5800	0	0
T102	234926	0	0	0
T103	78392	0	0	0
T104	489849	0	0	0
T105	1075	0	0	0
T106	684	0	0	0
T107	201033	0	0	0
T108	0	25	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	238298	0	0
T14	987338	0	0	0
T16	116171	0	0	0
T19	32900	0	0	0
T31	223484	3474	0	0
T32	0	1059	0	0
T34	0	7694	0	0
T49	0	13783	0	0
T96	0	5490	0	0
T97	0	5417	0	0
T98	0	8526	0	0
T99	0	15264	0	0
T100	0	1206	0	0
T101	0	6336	0	0
T102	234926	0	0	0
T103	78392	0	0	0
T104	489849	0	0	0
T105	1075	0	0	0
T106	684	0	0	0
T107	201033	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	239511	0	0
T14	987338	0	0	0
T16	116171	0	0	0
T19	32900	0	0	0
T31	223484	3678	0	0
T32	0	1005	0	0
T34	0	8306	0	0
T49	0	13664	0	0
T96	0	5171	0	0
T97	0	5473	0	0
T98	0	8575	0	0
T99	0	15103	0	0
T100	0	909	0	0
T101	0	6363	0	0
T102	234926	0	0	0
T103	78392	0	0	0
T104	489849	0	0	0
T105	1075	0	0	0
T106	684	0	0	0
T107	201033	0	0	0