Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 77352621 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 30557169 1 T1 18 T2 74 T3 146777



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 98629216 1 T1 18458 T2 173 T3 260092
values[0x0] 4392855 1 T1 13 T2 11 T3 49332
values[0x1] 4887719 1 T1 17 T2 14 T3 54721



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 53839982 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 54069808 1 T1 9182 T2 106 T3 218486



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 391561 1 T1 67 T3 1424 T4 2543
valid_sources[0x01] 422159 1 T1 82 T3 1433 T4 2484
valid_sources[0x02] 385800 1 T1 81 T3 1423 T4 2480
valid_sources[0x03] 453487 1 T1 86 T2 1 T3 1408
valid_sources[0x04] 406339 1 T1 71 T3 1424 T4 2501
valid_sources[0x05] 377033 1 T1 64 T3 1394 T4 2518
valid_sources[0x06] 392833 1 T1 74 T2 1 T3 1342
valid_sources[0x07] 449292 1 T1 72 T2 3 T3 1331
valid_sources[0x08] 383660 1 T1 64 T3 1430 T4 2479
valid_sources[0x09] 468255 1 T1 57 T2 1 T3 1508
valid_sources[0x0a] 413410 1 T1 76 T2 3 T3 1379
valid_sources[0x0b] 387359 1 T1 52 T3 1538 T4 2477
valid_sources[0x0c] 406472 1 T1 68 T2 1 T3 1365
valid_sources[0x0d] 404162 1 T1 67 T2 2 T3 1348
valid_sources[0x0e] 399339 1 T1 65 T3 1395 T4 2430
valid_sources[0x0f] 417265 1 T1 67 T3 1487 T4 2481
valid_sources[0x10] 429810 1 T1 49 T2 2 T3 1357
valid_sources[0x11] 417623 1 T1 79 T2 1 T3 1476
valid_sources[0x12] 409843 1 T1 97 T3 1451 T4 2478
valid_sources[0x13] 448855 1 T1 74 T3 1453 T4 2576
valid_sources[0x14] 383492 1 T1 82 T3 1399 T4 2499
valid_sources[0x15] 411171 1 T1 61 T2 3 T3 1445
valid_sources[0x16] 411054 1 T1 75 T2 2 T3 1406
valid_sources[0x17] 427884 1 T1 72 T3 1384 T4 2479
valid_sources[0x18] 467640 1 T1 72 T3 1432 T4 2492
valid_sources[0x19] 408251 1 T1 79 T3 1381 T4 2606
valid_sources[0x1a] 453747 1 T1 59 T2 3 T3 1400
valid_sources[0x1b] 454563 1 T1 57 T3 1467 T4 2501
valid_sources[0x1c] 436785 1 T1 70 T3 1430 T4 2485
valid_sources[0x1d] 435161 1 T1 69 T3 1428 T4 2330
valid_sources[0x1e] 383894 1 T1 66 T2 1 T3 1435
valid_sources[0x1f] 475159 1 T1 88 T2 4 T3 1384
valid_sources[0x20] 473559 1 T1 65 T2 2 T3 1481
valid_sources[0x21] 413597 1 T1 71 T2 2 T3 1440
valid_sources[0x22] 391395 1 T1 79 T3 1437 T4 2403
valid_sources[0x23] 457079 1 T1 54 T3 1456 T4 2466
valid_sources[0x24] 418627 1 T1 66 T3 1351 T4 2400
valid_sources[0x25] 403717 1 T1 67 T2 1 T3 1356
valid_sources[0x26] 396672 1 T1 66 T3 1419 T4 2478
valid_sources[0x27] 438217 1 T1 68 T3 1426 T4 2577
valid_sources[0x28] 396352 1 T1 74 T3 1461 T4 2475
valid_sources[0x29] 382106 1 T1 64 T3 1337 T4 2511
valid_sources[0x2a] 468886 1 T1 67 T3 1435 T4 2500
valid_sources[0x2b] 439643 1 T1 62 T3 1386 T4 2568
valid_sources[0x2c] 465123 1 T1 84 T3 1457 T4 2421
valid_sources[0x2d] 390300 1 T1 79 T3 1349 T4 2400
valid_sources[0x2e] 391387 1 T1 69 T2 2 T3 1360
valid_sources[0x2f] 418754 1 T1 82 T3 1434 T4 2518
valid_sources[0x30] 401241 1 T1 81 T3 1319 T4 2436
valid_sources[0x31] 410859 1 T1 63 T2 1 T3 1357
valid_sources[0x32] 453528 1 T1 78 T3 1396 T4 2511
valid_sources[0x33] 449774 1 T1 82 T2 1 T3 1389
valid_sources[0x34] 386070 1 T1 73 T3 1505 T4 2484
valid_sources[0x35] 411667 1 T1 86 T3 1361 T4 2420
valid_sources[0x36] 401097 1 T1 67 T2 2 T3 1409
valid_sources[0x37] 374493 1 T1 61 T3 1402 T4 2462
valid_sources[0x38] 400478 1 T1 70 T3 1488 T4 2526
valid_sources[0x39] 467100 1 T1 77 T3 1446 T4 2426
valid_sources[0x3a] 658294 1 T1 64 T3 1407 T4 2517
valid_sources[0x3b] 402384 1 T1 82 T2 2 T3 1466
valid_sources[0x3c] 425259 1 T1 81 T2 1 T3 1371
valid_sources[0x3d] 388519 1 T1 89 T2 1 T3 1419
valid_sources[0x3e] 395381 1 T1 86 T3 1456 T4 2439
valid_sources[0x3f] 385925 1 T1 63 T2 1 T3 1455
valid_sources[0x40] 435041 1 T1 61 T3 1421 T4 2504
valid_sources[0x41] 435643 1 T1 76 T3 1466 T4 2504
valid_sources[0x42] 468034 1 T1 71 T3 1387 T4 2464
valid_sources[0x43] 405232 1 T1 80 T3 1460 T4 2578
valid_sources[0x44] 402502 1 T1 63 T3 1335 T4 2562
valid_sources[0x45] 490768 1 T1 78 T2 2 T3 1477
valid_sources[0x46] 398991 1 T1 81 T2 1 T3 1459
valid_sources[0x47] 503531 1 T1 75 T3 1417 T4 2558
valid_sources[0x48] 401935 1 T1 63 T2 1 T3 1444
valid_sources[0x49] 396826 1 T1 74 T2 1 T3 1334
valid_sources[0x4a] 427459 1 T1 63 T3 1470 T4 2517
valid_sources[0x4b] 543115 1 T1 75 T2 2 T3 1477
valid_sources[0x4c] 403329 1 T1 74 T3 1384 T4 2673
valid_sources[0x4d] 400561 1 T1 67 T3 1432 T4 2519
valid_sources[0x4e] 441093 1 T1 66 T2 2 T3 1418
valid_sources[0x4f] 393643 1 T1 66 T2 5 T3 1474
valid_sources[0x50] 433019 1 T1 64 T3 1444 T4 2508
valid_sources[0x51] 398463 1 T1 85 T2 2 T3 1479
valid_sources[0x52] 395486 1 T1 79 T2 1 T3 1411
valid_sources[0x53] 416772 1 T1 80 T2 1 T3 1533
valid_sources[0x54] 398374 1 T1 73 T2 2 T3 1334
valid_sources[0x55] 402501 1 T1 78 T3 1493 T4 2604
valid_sources[0x56] 435605 1 T1 73 T2 1 T3 1529
valid_sources[0x57] 450425 1 T1 53 T3 1457 T4 2522
valid_sources[0x58] 432702 1 T1 70 T3 1340 T4 2549
valid_sources[0x59] 552600 1 T1 57 T3 1347 T4 2406
valid_sources[0x5a] 376928 1 T1 92 T2 1 T3 1504
valid_sources[0x5b] 411697 1 T1 71 T3 1453 T4 2494
valid_sources[0x5c] 437323 1 T1 81 T2 1 T3 1446
valid_sources[0x5d] 401735 1 T1 78 T2 1 T3 1512
valid_sources[0x5e] 423905 1 T1 72 T2 1 T3 1456
valid_sources[0x5f] 401822 1 T1 63 T3 1445 T4 2547
valid_sources[0x60] 509108 1 T1 73 T2 1 T3 1409
valid_sources[0x61] 396998 1 T1 74 T3 1528 T4 2425
valid_sources[0x62] 406696 1 T1 71 T3 1394 T4 2438
valid_sources[0x63] 385956 1 T1 66 T3 1443 T4 2462
valid_sources[0x64] 466121 1 T1 59 T2 3 T3 1464
valid_sources[0x65] 422132 1 T1 79 T3 1423 T4 2556
valid_sources[0x66] 457872 1 T1 76 T3 1397 T4 2586
valid_sources[0x67] 394970 1 T1 71 T3 1397 T4 2551
valid_sources[0x68] 427881 1 T1 66 T3 1384 T4 2541
valid_sources[0x69] 380755 1 T1 65 T2 2 T3 1422
valid_sources[0x6a] 461359 1 T1 75 T3 1445 T4 2436
valid_sources[0x6b] 395295 1 T1 71 T3 1456 T4 2551
valid_sources[0x6c] 400997 1 T1 60 T3 1347 T4 2437
valid_sources[0x6d] 371171 1 T1 68 T2 1 T3 1385
valid_sources[0x6e] 406017 1 T1 79 T2 2 T3 1498
valid_sources[0x6f] 403709 1 T1 70 T2 1 T3 1439
valid_sources[0x70] 412061 1 T1 69 T2 1 T3 1469
valid_sources[0x71] 413667 1 T1 45 T2 2 T3 1397
valid_sources[0x72] 430849 1 T1 58 T2 1 T3 1411
valid_sources[0x73] 408064 1 T1 64 T2 1 T3 1456
valid_sources[0x74] 415851 1 T1 64 T2 1 T3 1343
valid_sources[0x75] 421874 1 T1 74 T3 1422 T4 2471
valid_sources[0x76] 421311 1 T1 65 T3 1445 T4 2546
valid_sources[0x77] 409622 1 T1 85 T3 1469 T4 2461
valid_sources[0x78] 407802 1 T1 74 T3 1508 T4 2497
valid_sources[0x79] 554901 1 T1 79 T2 1 T3 1463
valid_sources[0x7a] 402383 1 T1 55 T2 1 T3 1340
valid_sources[0x7b] 471855 1 T1 83 T3 1429 T4 2490
valid_sources[0x7c] 382277 1 T1 93 T3 1449 T4 2415
valid_sources[0x7d] 423495 1 T1 89 T3 1475 T4 2452
valid_sources[0x7e] 406045 1 T1 43 T2 2 T3 1472
valid_sources[0x7f] 413202 1 T1 72 T2 2 T3 1439
valid_sources[0x80] 413923 1 T1 79 T3 1423 T4 2523



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 22387516 1 T2 66 T3 51620 T4 95430
values[0x0] all_enables biggest_size 4118537 1 T1 8 T2 4 T3 47915
values[0x1] all_enables biggest_size 4051116 1 T1 10 T2 4 T3 47242

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%