Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	13331347	0	0
ctrl_rd_A	2147483647	278878	0	0
intr_enable_rd_A	2147483647	248460	0	0
ovrd_rd_A	2147483647	277796	0	0
timeout_ctrl_rd_A	2147483647	276951	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13331347	0	0
T3	404264	161712	0	0
T4	836594	213990	0	0
T5	511972	191929	0	0
T6	326590	0	0	0
T7	172194	0	0	0
T8	184898	0	0	0
T9	221605	0	0	0
T10	145963	0	0	0
T11	326847	0	0	0
T12	0	106923	0	0
T14	0	199178	0	0
T21	0	68344	0	0
T22	0	353417	0	0
T23	0	266845	0	0
T24	0	170493	0	0
T25	0	92314	0	0
T26	662832	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	278878	0	0
T12	468833	12369	0	0
T21	0	7863	0	0
T24	0	9137	0	0
T30	148327	0	0	0
T31	101850	0	0	0
T35	0	29441	0	0
T80	0	4043	0	0
T81	0	9518	0	0
T82	0	1506	0	0
T83	0	10944	0	0
T84	0	3769	0	0
T85	0	3594	0	0
T86	4330	0	0	0
T87	474102	0	0	0
T88	863517	0	0	0
T89	55874	0	0	0
T90	306473	0	0	0
T91	142139	0	0	0
T92	62102	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	248460	0	0
T12	468833	10800	0	0
T21	0	6882	0	0
T24	0	8094	0	0
T30	148327	0	0	0
T31	101850	0	0	0
T80	0	3606	0	0
T81	0	8148	0	0
T82	0	1300	0	0
T83	0	9968	0	0
T84	0	3249	0	0
T86	4330	0	0	0
T87	474102	0	0	0
T88	863517	0	0	0
T89	55874	0	0	0
T90	306473	0	0	0
T91	142139	0	0	0
T92	62102	0	0	0
T93	0	5	0	0
T94	0	7	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	277796	0	0
T12	468833	12305	0	0
T21	0	7696	0	0
T24	0	9331	0	0
T30	148327	0	0	0
T31	101850	0	0	0
T35	0	30489	0	0
T80	0	3761	0	0
T81	0	9250	0	0
T82	0	1529	0	0
T83	0	11011	0	0
T84	0	3179	0	0
T85	0	3500	0	0
T86	4330	0	0	0
T87	474102	0	0	0
T88	863517	0	0	0
T89	55874	0	0	0
T90	306473	0	0	0
T91	142139	0	0	0
T92	62102	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	276951	0	0
T12	468833	11969	0	0
T21	0	7462	0	0
T24	0	8636	0	0
T30	148327	0	0	0
T31	101850	0	0	0
T35	0	29335	0	0
T80	0	4088	0	0
T81	0	9757	0	0
T82	0	1506	0	0
T83	0	10748	0	0
T84	0	3531	0	0
T85	0	3209	0	0
T86	4330	0	0	0
T87	474102	0	0	0
T88	863517	0	0	0
T89	55874	0	0	0
T90	306473	0	0	0
T91	142139	0	0	0
T92	62102	0	0	0