Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	67531054	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

27048385

1

T1

21321

T2

288

T3

172

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	84808714	1			T1	125771		T2	18148		T3	113974
values[0x0]	4619468	1			T1	1749		T2	59		T3	216
values[0x1]	5151257	1			T1	1741		T2	56		T3	225

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46747619	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

47831820

1

T1

54064

T2

6182

T3

37855

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	410416	1			T1	506		T4	33		T5	48
valid_sources[0x01]	355493	1			T1	531		T4	33		T5	30
valid_sources[0x02]	338504	1			T1	517		T4	42		T5	24
valid_sources[0x03]	416896	1			T1	484		T4	32		T5	38
valid_sources[0x04]	354340	1			T1	487		T4	37		T5	29
valid_sources[0x05]	383755	1			T1	481		T4	35		T5	36
valid_sources[0x06]	397186	1			T1	493		T4	37		T5	39
valid_sources[0x07]	337254	1			T1	531		T4	34		T5	29
valid_sources[0x08]	345416	1			T1	552		T4	44		T5	28
valid_sources[0x09]	348189	1			T1	517		T2	1333		T4	48
valid_sources[0x0a]	328768	1			T1	528		T4	48		T5	28
valid_sources[0x0b]	336231	1			T1	457		T4	35		T5	38
valid_sources[0x0c]	334047	1			T1	507		T4	30		T5	30
valid_sources[0x0d]	339518	1			T1	498		T4	44		T5	29
valid_sources[0x0e]	364547	1			T1	496		T4	37		T5	40
valid_sources[0x0f]	344111	1			T1	493		T4	44		T5	33
valid_sources[0x10]	343444	1			T1	506		T4	36		T5	31
valid_sources[0x11]	391126	1			T1	480		T4	32		T5	33
valid_sources[0x12]	358308	1			T1	504		T4	50		T5	24
valid_sources[0x13]	342534	1			T1	532		T2	1889		T4	49
valid_sources[0x14]	368976	1			T1	473		T4	39		T5	17
valid_sources[0x15]	375559	1			T1	532		T4	36		T5	26
valid_sources[0x16]	474022	1			T1	528		T4	29		T5	39
valid_sources[0x17]	357151	1			T1	545		T4	44		T5	27
valid_sources[0x18]	479322	1			T1	461		T4	37		T5	38
valid_sources[0x19]	391978	1			T1	495		T4	45		T5	25
valid_sources[0x1a]	342046	1			T1	520		T4	42		T5	34
valid_sources[0x1b]	404231	1			T1	523		T4	34		T5	30
valid_sources[0x1c]	341132	1			T1	504		T4	38		T5	31
valid_sources[0x1d]	392929	1			T1	491		T4	35		T5	36
valid_sources[0x1e]	362129	1			T1	471		T4	46		T5	31
valid_sources[0x1f]	359155	1			T1	479		T4	49		T5	44
valid_sources[0x20]	376710	1			T1	515		T4	52		T5	20
valid_sources[0x21]	410584	1			T1	495		T4	46		T5	34
valid_sources[0x22]	353270	1			T1	537		T4	33		T5	33
valid_sources[0x23]	352208	1			T1	519		T4	29		T5	32
valid_sources[0x24]	333922	1			T1	499		T4	32		T5	32
valid_sources[0x25]	392855	1			T1	519		T2	926		T4	35
valid_sources[0x26]	376145	1			T1	489		T4	46		T5	40
valid_sources[0x27]	332149	1			T1	498		T4	41		T5	31
valid_sources[0x28]	360144	1			T1	490		T4	40		T5	17
valid_sources[0x29]	343635	1			T1	505		T4	35		T5	24
valid_sources[0x2a]	411239	1			T1	503		T4	28		T5	28
valid_sources[0x2b]	376185	1			T1	515		T4	38		T5	34
valid_sources[0x2c]	358185	1			T1	514		T4	35		T5	23
valid_sources[0x2d]	336665	1			T1	479		T4	40		T5	29
valid_sources[0x2e]	372569	1			T1	495		T4	45		T5	34
valid_sources[0x2f]	349975	1			T1	490		T2	533		T4	37
valid_sources[0x30]	352675	1			T1	522		T4	39		T5	33
valid_sources[0x31]	400458	1			T1	514		T4	39		T5	31
valid_sources[0x32]	349035	1			T1	492		T4	33		T5	28
valid_sources[0x33]	428653	1			T1	496		T4	38		T5	21
valid_sources[0x34]	371780	1			T1	513		T4	40		T5	31
valid_sources[0x35]	363334	1			T1	476		T4	36		T5	35
valid_sources[0x36]	364544	1			T1	524		T4	35		T5	20
valid_sources[0x37]	375339	1			T1	486		T3	3531		T4	47
valid_sources[0x38]	394839	1			T1	500		T3	1		T4	35
valid_sources[0x39]	349914	1			T1	535		T4	50		T5	42
valid_sources[0x3a]	349406	1			T1	516		T4	42		T5	35
valid_sources[0x3b]	372947	1			T1	484		T4	50		T5	28
valid_sources[0x3c]	344777	1			T1	507		T4	41		T5	44
valid_sources[0x3d]	347063	1			T1	494		T4	35		T5	31
valid_sources[0x3e]	363680	1			T1	493		T4	47		T5	39
valid_sources[0x3f]	343799	1			T1	507		T4	42		T5	51
valid_sources[0x40]	387449	1			T1	472		T4	43		T5	25
valid_sources[0x41]	343243	1			T1	480		T4	36		T5	35
valid_sources[0x42]	348066	1			T1	532		T4	41		T5	20
valid_sources[0x43]	350070	1			T1	467		T4	34		T5	24
valid_sources[0x44]	364643	1			T1	541		T4	37		T5	49
valid_sources[0x45]	350194	1			T1	489		T4	27		T5	37
valid_sources[0x46]	381848	1			T1	490		T4	35		T5	28
valid_sources[0x47]	360448	1			T1	501		T4	43		T5	31
valid_sources[0x48]	339255	1			T1	513		T4	27		T5	19
valid_sources[0x49]	376536	1			T1	562		T4	36		T5	25
valid_sources[0x4a]	392092	1			T1	534		T4	37		T5	27
valid_sources[0x4b]	399991	1			T1	532		T4	42		T5	38
valid_sources[0x4c]	373979	1			T1	510		T4	43		T5	29
valid_sources[0x4d]	363497	1			T1	469		T4	39		T5	31
valid_sources[0x4e]	349176	1			T1	503		T4	34		T5	30
valid_sources[0x4f]	338271	1			T1	501		T4	45		T5	31
valid_sources[0x50]	614491	1			T1	531		T4	42		T5	24
valid_sources[0x51]	347399	1			T1	532		T4	45		T5	33
valid_sources[0x52]	360376	1			T1	516		T4	36		T5	48
valid_sources[0x53]	364210	1			T1	534		T4	48		T5	30
valid_sources[0x54]	362082	1			T1	485		T4	30		T5	28
valid_sources[0x55]	443903	1			T1	532		T4	27		T5	34
valid_sources[0x56]	379593	1			T1	523		T4	46		T5	30
valid_sources[0x57]	387754	1			T1	495		T4	33		T5	39
valid_sources[0x58]	335513	1			T1	499		T4	43		T5	34
valid_sources[0x59]	372283	1			T1	486		T4	39		T5	33
valid_sources[0x5a]	370959	1			T1	546		T4	45		T5	32
valid_sources[0x5b]	406064	1			T1	532		T4	32		T5	30
valid_sources[0x5c]	359391	1			T1	501		T3	5		T4	47
valid_sources[0x5d]	340924	1			T1	511		T4	43		T5	41
valid_sources[0x5e]	342902	1			T1	496		T4	31		T5	36
valid_sources[0x5f]	360444	1			T1	496		T4	40		T5	40
valid_sources[0x60]	342482	1			T1	486		T4	44		T5	26
valid_sources[0x61]	433928	1			T1	487		T4	39		T5	47
valid_sources[0x62]	359648	1			T1	480		T4	36		T5	28
valid_sources[0x63]	415827	1			T1	504		T4	45		T5	31
valid_sources[0x64]	398259	1			T1	503		T4	38		T5	32
valid_sources[0x65]	392255	1			T1	493		T4	42		T5	41
valid_sources[0x66]	347435	1			T1	492		T4	38		T5	16
valid_sources[0x67]	345916	1			T1	506		T4	27		T5	35
valid_sources[0x68]	346622	1			T1	479		T4	51		T5	36
valid_sources[0x69]	359419	1			T1	540		T4	35		T5	34
valid_sources[0x6a]	366543	1			T1	506		T4	33		T5	33
valid_sources[0x6b]	374942	1			T1	482		T4	37		T5	47
valid_sources[0x6c]	336748	1			T1	470		T4	46		T5	24
valid_sources[0x6d]	359548	1			T1	506		T4	36		T5	34
valid_sources[0x6e]	352523	1			T1	536		T4	32		T5	35
valid_sources[0x6f]	352779	1			T1	491		T4	52		T5	40
valid_sources[0x70]	403200	1			T1	465		T4	39		T5	29
valid_sources[0x71]	327332	1			T1	487		T4	32		T5	25
valid_sources[0x72]	342398	1			T1	462		T4	34		T5	40
valid_sources[0x73]	358073	1			T1	515		T4	47		T5	28
valid_sources[0x74]	349649	1			T1	504		T4	48		T5	35
valid_sources[0x75]	417373	1			T1	511		T4	30		T5	42
valid_sources[0x76]	346333	1			T1	512		T4	36		T5	41
valid_sources[0x77]	361691	1			T1	499		T4	27		T5	39
valid_sources[0x78]	366958	1			T1	493		T4	43		T5	23
valid_sources[0x79]	355088	1			T1	538		T4	44		T5	42
valid_sources[0x7a]	356112	1			T1	529		T4	44		T5	20
valid_sources[0x7b]	371766	1			T1	505		T4	40		T5	30
valid_sources[0x7c]	348355	1			T1	450		T2	2		T4	41
valid_sources[0x7d]	349904	1			T1	506		T4	38		T5	31
valid_sources[0x7e]	428943	1			T1	497		T4	50		T5	30
valid_sources[0x7f]	364554	1			T1	493		T4	40		T5	28
valid_sources[0x80]	387360	1			T1	509		T4	34		T5	40

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18372987

1

T1

20443

T2

245

T3

38

values[0x0]

all_enables

biggest_size

4366951

1

T1

586

T2

26

T3

90

values[0x1]

all_enables

biggest_size

4308447

1

T1

292

T2

17

T3

44