Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14273492	0	0
ctrl_rd_A	2147483647	280980	0	0
intr_enable_rd_A	2147483647	248792	0	0
ovrd_rd_A	2147483647	279746	0	0
timeout_ctrl_rd_A	2147483647	277169	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14273492	0	0
T8	165455	64566	0	0
T9	596850	0	0	0
T10	6325	0	0	0
T11	221954	0	0	0
T12	167508	0	0	0
T13	159165	0	0	0
T16	0	326501	0	0
T17	0	198596	0	0
T19	66248	0	0	0
T20	0	76429	0	0
T24	0	102758	0	0
T30	0	287712	0	0
T31	0	127879	0	0
T32	0	137143	0	0
T33	0	270521	0	0
T34	0	76417	0	0
T35	209155	0	0	0
T36	120820	0	0	0
T37	114148	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	280980	0	0
T15	476912	0	0	0
T20	0	8008	0	0
T24	325152	4466	0	0
T25	820	0	0	0
T31	0	3785	0	0
T32	0	15067	0	0
T40	544632	0	0	0
T87	250063	0	0	0
T104	0	12277	0	0
T105	0	3293	0	0
T106	0	2480	0	0
T107	0	24798	0	0
T108	0	6590	0	0
T109	0	6022	0	0
T110	939850	0	0	0
T111	362045	0	0	0
T112	138399	0	0	0
T113	154336	0	0	0
T114	959464	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	248792	0	0
T15	476912	0	0	0
T18	0	4	0	0
T20	0	6670	0	0
T24	325152	4000	0	0
T25	820	0	0	0
T31	0	3109	0	0
T32	0	13507	0	0
T40	544632	0	0	0
T87	250063	0	0	0
T104	0	10751	0	0
T105	0	2974	0	0
T106	0	2017	0	0
T107	0	22567	0	0
T110	939850	0	0	0
T111	362045	0	0	0
T112	138399	0	0	0
T113	154336	0	0	0
T114	959464	0	0	0
T115	0	18	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	279746	0	0
T15	476912	0	0	0
T20	0	7542	0	0
T24	325152	4514	0	0
T25	820	0	0	0
T31	0	3642	0	0
T32	0	15490	0	0
T40	544632	0	0	0
T87	250063	0	0	0
T104	0	13269	0	0
T105	0	3412	0	0
T106	0	2309	0	0
T107	0	24948	0	0
T108	0	6254	0	0
T109	0	6089	0	0
T110	939850	0	0	0
T111	362045	0	0	0
T112	138399	0	0	0
T113	154336	0	0	0
T114	959464	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	277169	0	0
T15	476912	0	0	0
T20	0	7424	0	0
T24	325152	4680	0	0
T25	820	0	0	0
T31	0	3602	0	0
T32	0	15672	0	0
T40	544632	0	0	0
T87	250063	0	0	0
T104	0	12719	0	0
T105	0	3413	0	0
T106	0	2194	0	0
T107	0	25587	0	0
T108	0	6310	0	0
T109	0	6079	0	0
T110	939850	0	0	0
T111	362045	0	0	0
T112	138399	0	0	0
T113	154336	0	0	0
T114	959464	0	0	0