Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 82429217 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 30709923 1 T1 117397 T2 80 T3 97



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 101696389 1 T1 276748 T2 351 T3 6255
values[0x0] 5404742 1 T1 486 T2 88 T3 85
values[0x1] 6038009 1 T1 500 T2 100 T3 68



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 56888623 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 56250517 1 T1 155244 T2 207 T3 2186



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 402476 1 T1 1433 T2 8 T3 25
valid_sources[0x01] 409993 1 T1 23 T2 2 T3 25
valid_sources[0x02] 402494 1 T1 1554 T3 23 T4 8
valid_sources[0x03] 446220 1 T1 4 T2 1 T3 26
valid_sources[0x04] 414003 1 T1 3 T3 18 T4 10
valid_sources[0x05] 435991 1 T1 16 T3 23 T4 8
valid_sources[0x06] 413950 1 T1 39 T2 4 T3 24
valid_sources[0x07] 427066 1 T1 2 T3 21 T4 3
valid_sources[0x08] 468321 1 T1 1 T3 27 T4 2
valid_sources[0x09] 439177 1 T1 97 T2 9 T3 34
valid_sources[0x0a] 467535 1 T1 48 T2 2 T3 24
valid_sources[0x0b] 455955 1 T1 23 T3 28 T4 3
valid_sources[0x0c] 446233 1 T1 48 T3 29 T4 5
valid_sources[0x0d] 410837 1 T1 6 T2 2 T3 20
valid_sources[0x0e] 437147 1 T1 77 T2 6 T3 16
valid_sources[0x0f] 446519 1 T1 3085 T2 18 T3 39
valid_sources[0x10] 423342 1 T1 1637 T3 19 T4 3
valid_sources[0x11] 424401 1 T1 26 T3 25 T4 5
valid_sources[0x12] 445475 1 T1 621 T3 18 T4 8
valid_sources[0x13] 416817 1 T1 28 T2 12 T3 28
valid_sources[0x14] 448598 1 T1 51 T2 2 T3 23
valid_sources[0x15] 468131 1 T1 7 T3 27 T4 8
valid_sources[0x16] 413848 1 T1 2 T3 28 T4 10
valid_sources[0x17] 427059 1 T1 77 T2 18 T3 21
valid_sources[0x18] 434036 1 T1 962 T2 1 T3 24
valid_sources[0x19] 457122 1 T1 1 T3 25 T5 118
valid_sources[0x1a] 433594 1 T1 30 T2 3 T3 25
valid_sources[0x1b] 451000 1 T1 2 T3 24 T4 4
valid_sources[0x1c] 394986 1 T3 22 T4 3 T5 622
valid_sources[0x1d] 436314 1 T1 47 T2 21 T3 23
valid_sources[0x1e] 427942 1 T1 4 T2 2 T3 17
valid_sources[0x1f] 420020 1 T1 3 T3 29 T4 3
valid_sources[0x20] 412916 1 T1 24 T3 20 T4 3
valid_sources[0x21] 432756 1 T1 440 T3 20 T4 5
valid_sources[0x22] 418006 1 T1 5 T3 28 T4 6
valid_sources[0x23] 453267 1 T1 438 T2 2 T3 14
valid_sources[0x24] 535578 1 T1 3074 T2 1 T3 21
valid_sources[0x25] 420221 1 T1 4079 T2 7 T3 36
valid_sources[0x26] 415040 1 T2 2 T3 34 T4 5
valid_sources[0x27] 509290 1 T1 23 T2 2 T3 20
valid_sources[0x28] 421654 1 T1 1 T2 7 T3 28
valid_sources[0x29] 452059 1 T1 37 T3 21 T4 2
valid_sources[0x2a] 418212 1 T1 35 T2 4 T3 28
valid_sources[0x2b] 413052 1 T1 3 T2 10 T3 22
valid_sources[0x2c] 427954 1 T1 420 T2 9 T3 23
valid_sources[0x2d] 493264 1 T1 18 T3 30 T5 349
valid_sources[0x2e] 494717 1 T1 1275 T3 28 T4 9
valid_sources[0x2f] 440753 1 T1 1 T2 7 T3 29
valid_sources[0x30] 424914 1 T1 1 T2 5 T3 36
valid_sources[0x31] 484506 1 T1 2857 T3 32 T4 6
valid_sources[0x32] 426436 1 T2 2 T3 25 T4 8
valid_sources[0x33] 440274 1 T1 54 T3 20 T4 1
valid_sources[0x34] 447338 1 T1 57 T3 22 T4 6
valid_sources[0x35] 420648 1 T1 27 T3 30 T4 1
valid_sources[0x36] 409540 1 T1 422 T2 1 T3 16
valid_sources[0x37] 482408 1 T1 2 T3 26 T4 1
valid_sources[0x38] 479204 1 T1 5 T2 9 T3 33
valid_sources[0x39] 446865 1 T1 13 T2 8 T3 26
valid_sources[0x3a] 464203 1 T1 87 T2 1 T3 25
valid_sources[0x3b] 427486 1 T1 7 T2 11 T3 31
valid_sources[0x3c] 426631 1 T1 6 T3 29 T4 8
valid_sources[0x3d] 436941 1 T1 31 T2 9 T3 21
valid_sources[0x3e] 432592 1 T3 28 T4 6 T5 193
valid_sources[0x3f] 453846 1 T1 72 T3 16 T5 250
valid_sources[0x40] 427515 1 T1 6 T2 6 T3 36
valid_sources[0x41] 452783 1 T1 81 T2 2 T3 29
valid_sources[0x42] 438249 1 T1 2268 T3 20 T4 5
valid_sources[0x43] 425767 1 T1 1 T3 21 T4 9
valid_sources[0x44] 443548 1 T1 18 T3 30 T4 1
valid_sources[0x45] 420045 1 T1 402 T2 3 T3 25
valid_sources[0x46] 464040 1 T1 3357 T3 16 T4 1
valid_sources[0x47] 445464 1 T1 165 T3 29 T4 9
valid_sources[0x48] 418336 1 T1 8 T3 21 T5 162
valid_sources[0x49] 409666 1 T1 1762 T3 21 T4 4
valid_sources[0x4a] 414990 1 T1 1294 T3 23 T4 6
valid_sources[0x4b] 423015 1 T1 8 T2 3 T3 28
valid_sources[0x4c] 415471 1 T1 3 T3 26 T4 1
valid_sources[0x4d] 474587 1 T1 5 T3 25 T4 4
valid_sources[0x4e] 415683 1 T1 82 T3 36 T4 2
valid_sources[0x4f] 441313 1 T1 55 T3 23 T4 4
valid_sources[0x50] 479475 1 T1 64 T3 23 T4 11
valid_sources[0x51] 470830 1 T1 2531 T3 18 T4 6
valid_sources[0x52] 416362 1 T1 1252 T3 21 T4 5
valid_sources[0x53] 450706 1 T1 60 T2 5 T3 22
valid_sources[0x54] 448384 1 T1 10506 T3 21 T4 3
valid_sources[0x55] 410283 1 T1 49 T3 21 T4 9
valid_sources[0x56] 422099 1 T1 460 T3 23 T4 6
valid_sources[0x57] 442935 1 T3 31 T5 839 T6 13
valid_sources[0x58] 442039 1 T1 27 T3 23 T4 3
valid_sources[0x59] 467728 1 T1 28 T2 3 T3 24
valid_sources[0x5a] 417822 1 T1 9575 T3 26 T5 419
valid_sources[0x5b] 535955 1 T1 95 T2 9 T3 31
valid_sources[0x5c] 420454 1 T1 6 T2 4 T3 20
valid_sources[0x5d] 434788 1 T1 58 T3 30 T4 6
valid_sources[0x5e] 421529 1 T1 27 T3 27 T4 6
valid_sources[0x5f] 497976 1 T1 2743 T2 1 T3 19
valid_sources[0x60] 420814 1 T1 2 T2 2 T3 29
valid_sources[0x61] 562765 1 T1 23 T3 21 T4 5
valid_sources[0x62] 408751 1 T1 1 T2 1 T3 23
valid_sources[0x63] 418584 1 T1 2 T3 26 T4 2
valid_sources[0x64] 434852 1 T1 14 T2 5 T3 21
valid_sources[0x65] 442177 1 T1 4907 T3 25 T4 4
valid_sources[0x66] 421366 1 T1 2 T2 15 T3 25
valid_sources[0x67] 419453 1 T1 8 T2 1 T3 22
valid_sources[0x68] 475405 1 T1 3 T3 23 T4 2
valid_sources[0x69] 443644 1 T1 4 T3 26 T4 5
valid_sources[0x6a] 438907 1 T1 29 T2 20 T3 30
valid_sources[0x6b] 426151 1 T1 52 T3 29 T4 5
valid_sources[0x6c] 413176 1 T1 689 T2 4 T3 20
valid_sources[0x6d] 432551 1 T1 5759 T3 24 T4 3
valid_sources[0x6e] 437596 1 T1 1 T3 30 T4 1
valid_sources[0x6f] 400562 1 T1 59 T2 1 T3 27
valid_sources[0x70] 483656 1 T1 519 T3 15 T4 8
valid_sources[0x71] 616045 1 T1 31 T2 2 T3 29
valid_sources[0x72] 413528 1 T1 431 T3 24 T4 2
valid_sources[0x73] 432936 1 T1 8586 T2 6 T3 24
valid_sources[0x74] 431219 1 T1 2 T3 16 T4 2
valid_sources[0x75] 480839 1 T1 107 T2 2 T3 26
valid_sources[0x76] 409660 1 T1 12 T3 32 T4 2
valid_sources[0x77] 417817 1 T1 2 T3 20 T4 3
valid_sources[0x78] 419684 1 T1 405 T2 2 T3 26
valid_sources[0x79] 463871 1 T1 1 T3 29 T4 1
valid_sources[0x7a] 445914 1 T1 3864 T3 28 T4 6
valid_sources[0x7b] 418121 1 T1 946 T3 26 T4 9
valid_sources[0x7c] 422562 1 T3 29 T4 1 T5 555
valid_sources[0x7d] 429798 1 T1 403 T3 22 T4 12
valid_sources[0x7e] 428971 1 T1 52 T3 32 T4 1
valid_sources[0x7f] 438355 1 T1 399 T3 28 T4 9
valid_sources[0x80] 458933 1 T1 39 T3 18 T4 9



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 20533535 1 T1 117048 T2 21 T3 46
values[0x0] all_enables biggest_size 5116634 1 T1 224 T2 36 T3 34
values[0x1] all_enables biggest_size 5059754 1 T1 125 T2 23 T3 17

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%