Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	16759582	0	0
ctrl_rd_A	2147483647	303186	0	0
intr_enable_rd_A	2147483647	269021	0	0
ovrd_rd_A	2147483647	303552	0	0
timeout_ctrl_rd_A	2147483647	304401	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16759582	0	0
T5	483452	113994	0	0
T6	361191	0	0	0
T7	888223	352841	0	0
T8	1074	0	0	0
T9	152597	0	0	0
T10	835977	0	0	0
T11	15712	0	0	0
T12	160217	0	0	0
T13	0	151328	0	0
T14	0	115879	0	0
T18	207245	0	0	0
T19	0	142521	0	0
T20	869882	0	0	0
T28	0	201737	0	0
T29	0	239130	0	0
T30	0	385020	0	0
T31	0	43944	0	0
T32	0	181995	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	303186	0	0
T19	619968	16526	0	0
T31	0	5029	0	0
T32	0	10269	0	0
T36	604833	0	0	0
T94	0	2672	0	0
T95	0	3623	0	0
T96	0	9710	0	0
T97	0	3056	0	0
T98	0	11644	0	0
T99	0	6023	0	0
T100	0	22674	0	0
T101	111826	0	0	0
T102	603067	0	0	0
T103	604651	0	0	0
T104	33543	0	0	0
T105	405219	0	0	0
T106	419731	0	0	0
T107	146147	0	0	0
T108	298720	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	269021	0	0
T19	619968	13927	0	0
T31	0	4324	0	0
T32	0	9110	0	0
T36	604833	0	0	0
T94	0	2257	0	0
T95	0	3180	0	0
T96	0	8592	0	0
T97	0	2790	0	0
T98	0	10255	0	0
T99	0	5511	0	0
T100	0	21591	0	0
T101	111826	0	0	0
T102	603067	0	0	0
T103	604651	0	0	0
T104	33543	0	0	0
T105	405219	0	0	0
T106	419731	0	0	0
T107	146147	0	0	0
T108	298720	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	303552	0	0
T19	619968	15689	0	0
T31	0	5210	0	0
T32	0	10152	0	0
T36	604833	0	0	0
T94	0	2476	0	0
T95	0	3445	0	0
T96	0	9481	0	0
T97	0	3188	0	0
T98	0	12071	0	0
T99	0	6077	0	0
T100	0	24008	0	0
T101	111826	0	0	0
T102	603067	0	0	0
T103	604651	0	0	0
T104	33543	0	0	0
T105	405219	0	0	0
T106	419731	0	0	0
T107	146147	0	0	0
T108	298720	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	304401	0	0
T19	619968	16135	0	0
T31	0	5242	0	0
T32	0	10205	0	0
T36	604833	0	0	0
T94	0	2665	0	0
T95	0	3912	0	0
T96	0	9841	0	0
T97	0	3165	0	0
T98	0	12499	0	0
T99	0	5903	0	0
T100	0	24479	0	0
T101	111826	0	0	0
T102	603067	0	0	0
T103	604651	0	0	0
T104	33543	0	0	0
T105	405219	0	0	0
T106	419731	0	0	0
T107	146147	0	0	0
T108	298720	0	0	0