Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	77996582	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

28280245

1

T1

305484

T2

275

T3

168

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	96078727	1			T1	241973		T2	1374		T3	540
values[0x0]	4821699	1			T1	99957		T2	92		T3	163
values[0x1]	5376401	1			T1	111990		T2	77		T3	145

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	53803490	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

52473337

1

T1

353650

T2

645

T3

326

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	495124	1			T1	1894		T2	7		T3	1
valid_sources[0x01]	384831	1			T1	1758		T2	6		T3	2
valid_sources[0x02]	407964	1			T1	1566		T2	8		T3	4
valid_sources[0x03]	384261	1			T1	1745		T2	8		T3	4
valid_sources[0x04]	444743	1			T1	1651		T2	4		T6	426
valid_sources[0x05]	382774	1			T1	1757		T2	6		T3	6
valid_sources[0x06]	394596	1			T1	1755		T2	5		T3	6
valid_sources[0x07]	370522	1			T1	1915		T2	6		T3	2
valid_sources[0x08]	421127	1			T1	1617		T2	14		T3	1
valid_sources[0x09]	424593	1			T1	1850		T2	5		T3	1
valid_sources[0x0a]	421927	1			T1	1792		T2	2		T3	6
valid_sources[0x0b]	374133	1			T1	1756		T2	5		T6	428
valid_sources[0x0c]	392028	1			T1	1829		T2	6		T3	6
valid_sources[0x0d]	524287	1			T1	1874		T2	6		T3	3
valid_sources[0x0e]	385349	1			T1	1760		T2	9		T3	1
valid_sources[0x0f]	427966	1			T1	1809		T2	8		T3	2
valid_sources[0x10]	398009	1			T1	1825		T2	8		T3	5
valid_sources[0x11]	411960	1			T1	1732		T2	6		T3	5
valid_sources[0x12]	381899	1			T1	1777		T2	9		T3	2
valid_sources[0x13]	388659	1			T1	1702		T2	3		T3	7
valid_sources[0x14]	419405	1			T1	1682		T2	8		T3	2
valid_sources[0x15]	390979	1			T1	1798		T2	9		T3	2
valid_sources[0x16]	426490	1			T1	1849		T2	5		T3	5
valid_sources[0x17]	446092	1			T1	1771		T2	5		T3	1
valid_sources[0x18]	398936	1			T1	1869		T2	14		T3	1
valid_sources[0x19]	442858	1			T1	2090		T2	8		T3	3
valid_sources[0x1a]	428012	1			T1	1829		T2	4		T3	8
valid_sources[0x1b]	411867	1			T1	1818		T2	7		T6	429
valid_sources[0x1c]	421422	1			T1	1816		T2	5		T3	3
valid_sources[0x1d]	429423	1			T1	1894		T2	9		T3	1
valid_sources[0x1e]	392263	1			T1	1778		T2	8		T6	431
valid_sources[0x1f]	415218	1			T1	1785		T2	7		T3	1
valid_sources[0x20]	464151	1			T1	1811		T2	3		T3	1
valid_sources[0x21]	383311	1			T1	1840		T2	7		T3	2
valid_sources[0x22]	383027	1			T1	1847		T2	6		T3	2
valid_sources[0x23]	484640	1			T1	1793		T2	14		T3	7
valid_sources[0x24]	404572	1			T1	1711		T2	7		T6	393
valid_sources[0x25]	388167	1			T1	1905		T2	5		T3	5
valid_sources[0x26]	397374	1			T1	1850		T2	12		T3	6
valid_sources[0x27]	386647	1			T1	1737		T2	4		T3	2
valid_sources[0x28]	397402	1			T1	1903		T2	4		T3	7
valid_sources[0x29]	436847	1			T1	1778		T2	11		T3	3
valid_sources[0x2a]	387544	1			T1	1780		T2	2		T3	3
valid_sources[0x2b]	380313	1			T1	1731		T2	2		T3	3
valid_sources[0x2c]	386056	1			T1	1722		T2	6		T3	5
valid_sources[0x2d]	425236	1			T1	1666		T2	4		T3	6
valid_sources[0x2e]	395376	1			T1	1739		T2	5		T3	5
valid_sources[0x2f]	494417	1			T1	1830		T2	6		T3	4
valid_sources[0x30]	392375	1			T1	1968		T2	3		T3	1
valid_sources[0x31]	435549	1			T1	1824		T2	7		T3	4
valid_sources[0x32]	371619	1			T1	1820		T2	5		T3	2
valid_sources[0x33]	388188	1			T1	1750		T2	4		T3	2
valid_sources[0x34]	388677	1			T1	1700		T2	10		T3	2
valid_sources[0x35]	385196	1			T1	1801		T2	9		T3	2
valid_sources[0x36]	400914	1			T1	1923		T2	7		T3	2
valid_sources[0x37]	496138	1			T1	1755		T2	8		T3	3
valid_sources[0x38]	392210	1			T1	1791		T2	5		T3	2
valid_sources[0x39]	380173	1			T1	1777		T2	7		T3	2
valid_sources[0x3a]	391596	1			T1	1761		T2	8		T3	1
valid_sources[0x3b]	405742	1			T1	1808		T2	11		T3	5
valid_sources[0x3c]	376486	1			T1	1893		T2	6		T3	4
valid_sources[0x3d]	398464	1			T1	1711		T2	8		T3	3
valid_sources[0x3e]	444064	1			T1	1829		T2	7		T3	5
valid_sources[0x3f]	437005	1			T1	1751		T2	6		T3	3
valid_sources[0x40]	387812	1			T1	1809		T2	5		T3	4
valid_sources[0x41]	384228	1			T1	1712		T2	5		T3	5
valid_sources[0x42]	397290	1			T1	1689		T2	6		T3	7
valid_sources[0x43]	431171	1			T1	1676		T2	3		T3	4
valid_sources[0x44]	388386	1			T1	1792		T2	3		T3	3
valid_sources[0x45]	445301	1			T1	1849		T2	4		T3	1
valid_sources[0x46]	412148	1			T1	1790		T2	4		T3	5
valid_sources[0x47]	406122	1			T1	1740		T2	6		T3	1
valid_sources[0x48]	396292	1			T1	1801		T2	7		T6	415
valid_sources[0x49]	387751	1			T1	1723		T2	4		T3	2
valid_sources[0x4a]	396048	1			T1	1796		T2	7		T3	1
valid_sources[0x4b]	381530	1			T1	1800		T3	5		T6	473
valid_sources[0x4c]	386055	1			T1	1807		T2	5		T3	5
valid_sources[0x4d]	442264	1			T1	1816		T2	12		T3	2
valid_sources[0x4e]	394432	1			T1	1686		T2	12		T3	9
valid_sources[0x4f]	391543	1			T1	1800		T2	4		T3	5
valid_sources[0x50]	379017	1			T1	1755		T2	5		T3	4
valid_sources[0x51]	395494	1			T1	1770		T2	4		T3	4
valid_sources[0x52]	381797	1			T1	1828		T2	3		T3	1
valid_sources[0x53]	376112	1			T1	1723		T2	6		T3	2
valid_sources[0x54]	468453	1			T1	1653		T2	6		T3	6
valid_sources[0x55]	429525	1			T1	1702		T2	6		T3	1
valid_sources[0x56]	376452	1			T1	1758		T2	4		T3	8
valid_sources[0x57]	386448	1			T1	1827		T2	7		T3	5
valid_sources[0x58]	377680	1			T1	1707		T2	5		T3	4
valid_sources[0x59]	387986	1			T1	1843		T2	3		T3	2
valid_sources[0x5a]	431581	1			T1	1726		T2	7		T3	4
valid_sources[0x5b]	387411	1			T1	1975		T2	4		T3	7
valid_sources[0x5c]	397071	1			T1	1753		T2	6		T3	7
valid_sources[0x5d]	442140	1			T1	1957		T2	5		T6	396
valid_sources[0x5e]	439352	1			T1	1724		T2	6		T3	6
valid_sources[0x5f]	376216	1			T1	1790		T2	8		T3	4
valid_sources[0x60]	400694	1			T1	1688		T2	8		T6	416
valid_sources[0x61]	389080	1			T1	1665		T2	4		T3	1
valid_sources[0x62]	380871	1			T1	1630		T2	8		T3	3
valid_sources[0x63]	395996	1			T1	1945		T2	3		T3	1
valid_sources[0x64]	395311	1			T1	1610		T2	10		T3	6
valid_sources[0x65]	448375	1			T1	1806		T2	4		T6	397
valid_sources[0x66]	386145	1			T1	1793		T2	4		T3	5
valid_sources[0x67]	465444	1			T1	1782		T2	3		T3	4
valid_sources[0x68]	538962	1			T1	1776		T2	6		T3	6
valid_sources[0x69]	406350	1			T1	1871		T2	6		T3	5
valid_sources[0x6a]	401128	1			T1	1752		T2	7		T3	2
valid_sources[0x6b]	387777	1			T1	1935		T2	5		T3	2
valid_sources[0x6c]	403732	1			T1	1622		T2	10		T6	411
valid_sources[0x6d]	499946	1			T1	1722		T2	5		T3	3
valid_sources[0x6e]	398830	1			T1	1804		T2	6		T6	356
valid_sources[0x6f]	531352	1			T1	1656		T2	6		T3	2
valid_sources[0x70]	390387	1			T1	1786		T2	12		T3	5
valid_sources[0x71]	375903	1			T1	1765		T2	8		T3	9
valid_sources[0x72]	471337	1			T1	1753		T2	5		T3	2
valid_sources[0x73]	381526	1			T1	1654		T2	3		T3	5
valid_sources[0x74]	473623	1			T1	1881		T2	9		T3	4
valid_sources[0x75]	459895	1			T1	1682		T3	6		T6	399
valid_sources[0x76]	398094	1			T1	1775		T2	5		T3	5
valid_sources[0x77]	401158	1			T1	1792		T2	7		T3	1
valid_sources[0x78]	401671	1			T1	1712		T2	5		T3	4
valid_sources[0x79]	417221	1			T1	1822		T2	9		T3	2
valid_sources[0x7a]	386321	1			T1	1837		T2	4		T6	426
valid_sources[0x7b]	393180	1			T1	1793		T2	7		T3	2
valid_sources[0x7c]	442396	1			T1	1713		T2	7		T3	3
valid_sources[0x7d]	391065	1			T1	1717		T2	7		T6	406
valid_sources[0x7e]	410042	1			T1	1728		T2	6		T3	1
valid_sources[0x7f]	373885	1			T1	1706		T2	3		T3	3
valid_sources[0x80]	409225	1			T1	1773		T2	4		T3	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19235612

1

T1

108988

T2

204

T3

68

values[0x0]

all_enables

biggest_size

4552975

1

T1

98598

T2

45

T3

73

values[0x1]

all_enables

biggest_size

4491658

1

T1

97898

T2

26

T3

27