Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14867057	0	0
ctrl_rd_A	2147483647	257340	0	0
intr_enable_rd_A	2147483647	228572	0	0
ovrd_rd_A	2147483647	255304	0	0
timeout_ctrl_rd_A	2147483647	257534	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14867057	0	0
T1	117062	334620	0	0
T2	281099	0	0	0
T3	399695	0	0	0
T4	138579	0	0	0
T5	883	0	0	0
T6	364233	0	0	0
T7	1027	0	0	0
T8	624458	0	0	0
T9	515853	0	0	0
T10	781069	0	0	0
T20	0	117405	0	0
T27	0	88462	0	0
T28	0	86218	0	0
T35	0	86348	0	0
T36	0	43764	0	0
T37	0	42680	0	0
T38	0	159389	0	0
T39	0	151389	0	0
T40	0	37998	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	257340	0	0
T27	317759	7108	0	0
T36	0	5426	0	0
T46	0	6655	0	0
T91	0	4469	0	0
T92	0	5209	0	0
T93	0	7087	0	0
T94	0	15435	0	0
T95	0	16280	0	0
T96	0	14865	0	0
T97	0	1721	0	0
T98	161134	0	0	0
T99	154518	0	0	0
T100	124274	0	0	0
T101	170600	0	0	0
T102	125644	0	0	0
T103	837159	0	0	0
T104	153067	0	0	0
T105	172055	0	0	0
T106	719705	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	228572	0	0
T17	771934	0	0	0
T18	238341	22	0	0
T23	50864	0	0	0
T27	0	5682	0	0
T30	172607	0	0	0
T31	3099	0	0	0
T36	0	4692	0	0
T46	0	6018	0	0
T85	190875	0	0	0
T86	201574	0	0	0
T87	184151	0	0	0
T88	44509	0	0	0
T89	106173	0	0	0
T91	0	3889	0	0
T92	0	4667	0	0
T93	0	6250	0	0
T94	0	13565	0	0
T95	0	14910	0	0
T96	0	13472	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	255304	0	0
T27	317759	6949	0	0
T36	0	5369	0	0
T46	0	6476	0	0
T91	0	4349	0	0
T92	0	4940	0	0
T93	0	7217	0	0
T94	0	14988	0	0
T95	0	16870	0	0
T96	0	15619	0	0
T97	0	1883	0	0
T98	161134	0	0	0
T99	154518	0	0	0
T100	124274	0	0	0
T101	170600	0	0	0
T102	125644	0	0	0
T103	837159	0	0	0
T104	153067	0	0	0
T105	172055	0	0	0
T106	719705	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	257534	0	0
T27	317759	7218	0	0
T36	0	5278	0	0
T46	0	6913	0	0
T91	0	4475	0	0
T92	0	5255	0	0
T93	0	7035	0	0
T94	0	15114	0	0
T95	0	16780	0	0
T96	0	15384	0	0
T97	0	2042	0	0
T98	161134	0	0	0
T99	154518	0	0	0
T100	124274	0	0	0
T101	170600	0	0	0
T102	125644	0	0	0
T103	837159	0	0	0
T104	153067	0	0	0
T105	172055	0	0	0
T106	719705	0	0	0