Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	70025026	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

28603018

1

T1

98

T2

198

T3

382

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	88183691	1			T1	812		T2	1683		T3	6698
values[0x0]	4933985	1			T1	131		T2	190		T3	175
values[0x1]	5510368	1			T1	126		T2	210		T3	156

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	48531817	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

50096227

1

T1

366

T2

734

T3

2543

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	345879	1			T2	8		T4	398		T5	1
valid_sources[0x01]	444293	1			T2	11		T4	405		T5	2
valid_sources[0x02]	359781	1			T2	4		T4	360		T7	58
valid_sources[0x03]	382746	1			T2	10		T4	340		T5	1
valid_sources[0x04]	388935	1			T2	3		T4	342		T7	56
valid_sources[0x05]	382836	1			T2	5		T4	371		T5	4
valid_sources[0x06]	437787	1			T2	6		T4	363		T5	1
valid_sources[0x07]	373120	1			T2	10		T4	392		T5	1
valid_sources[0x08]	369115	1			T2	5		T4	344		T7	55
valid_sources[0x09]	409646	1			T2	6		T4	378		T5	6
valid_sources[0x0a]	375884	1			T2	5		T4	345		T5	5
valid_sources[0x0b]	368986	1			T2	18		T4	385		T7	36
valid_sources[0x0c]	387437	1			T2	7		T4	354		T5	2
valid_sources[0x0d]	405599	1			T2	7		T4	376		T5	2
valid_sources[0x0e]	399871	1			T2	10		T4	358		T7	17
valid_sources[0x0f]	381285	1			T2	11		T4	376		T7	45
valid_sources[0x10]	388660	1			T2	9		T4	353		T5	1
valid_sources[0x11]	409890	1			T2	5		T4	355		T5	2
valid_sources[0x12]	373826	1			T2	4		T4	380		T5	2
valid_sources[0x13]	380020	1			T2	13		T4	328		T5	1
valid_sources[0x14]	378474	1			T2	15		T4	352		T5	2
valid_sources[0x15]	375476	1			T2	10		T4	357		T7	78
valid_sources[0x16]	360962	1			T2	10		T4	357		T7	50
valid_sources[0x17]	448124	1			T2	12		T4	352		T7	87
valid_sources[0x18]	379127	1			T2	9		T4	334		T5	1
valid_sources[0x19]	401636	1			T2	16		T4	382		T7	42
valid_sources[0x1a]	371193	1			T2	11		T4	323		T5	6
valid_sources[0x1b]	363570	1			T2	7		T4	362		T7	48
valid_sources[0x1c]	367525	1			T2	9		T4	373		T5	1
valid_sources[0x1d]	355606	1			T2	8		T4	349		T5	3
valid_sources[0x1e]	366354	1			T2	9		T4	348		T5	1
valid_sources[0x1f]	479196	1			T2	10		T4	322		T5	1
valid_sources[0x20]	369529	1			T2	15		T4	336		T5	1
valid_sources[0x21]	383802	1			T2	7		T4	347		T7	68
valid_sources[0x22]	367233	1			T2	5		T4	354		T7	48
valid_sources[0x23]	373753	1			T2	10		T4	352		T7	47
valid_sources[0x24]	354377	1			T2	9		T4	356		T5	2
valid_sources[0x25]	378256	1			T2	8		T4	370		T5	2
valid_sources[0x26]	382308	1			T2	8		T4	354		T7	27
valid_sources[0x27]	351374	1			T2	8		T4	331		T5	1
valid_sources[0x28]	407594	1			T2	5		T4	346		T5	1
valid_sources[0x29]	380872	1			T2	12		T4	351		T5	1
valid_sources[0x2a]	543160	1			T2	9		T4	360		T5	1
valid_sources[0x2b]	386048	1			T2	5		T4	370		T5	1
valid_sources[0x2c]	372463	1			T2	5		T4	352		T5	2
valid_sources[0x2d]	405473	1			T2	4		T4	363		T7	45
valid_sources[0x2e]	436011	1			T2	15		T4	381		T5	1
valid_sources[0x2f]	370699	1			T2	7		T4	379		T5	2
valid_sources[0x30]	374811	1			T2	5		T4	380		T7	37
valid_sources[0x31]	373227	1			T2	6		T4	372		T7	42
valid_sources[0x32]	369260	1			T2	10		T4	334		T5	1
valid_sources[0x33]	380232	1			T2	7		T4	352		T5	2
valid_sources[0x34]	370124	1			T2	9		T4	371		T5	2
valid_sources[0x35]	397735	1			T2	13		T4	365		T7	40
valid_sources[0x36]	361595	1			T2	7		T4	327		T5	1
valid_sources[0x37]	408534	1			T2	7		T4	340		T5	2
valid_sources[0x38]	385849	1			T2	3		T4	352		T7	36
valid_sources[0x39]	376417	1			T2	4		T4	343		T5	1
valid_sources[0x3a]	447698	1			T2	10		T4	345		T7	55
valid_sources[0x3b]	366251	1			T2	6		T4	345		T5	1
valid_sources[0x3c]	405536	1			T2	5		T4	370		T5	3
valid_sources[0x3d]	378598	1			T2	5		T3	6187		T4	374
valid_sources[0x3e]	386340	1			T2	5		T4	358		T5	1
valid_sources[0x3f]	368588	1			T2	7		T4	357		T5	1
valid_sources[0x40]	406065	1			T1	1069		T2	11		T4	337
valid_sources[0x41]	368018	1			T2	8		T4	355		T5	1
valid_sources[0x42]	374640	1			T2	7		T4	361		T7	51
valid_sources[0x43]	378325	1			T2	8		T4	353		T7	60
valid_sources[0x44]	408979	1			T2	7		T4	373		T5	1
valid_sources[0x45]	362325	1			T2	18		T4	341		T5	1
valid_sources[0x46]	363086	1			T2	11		T4	380		T5	3
valid_sources[0x47]	364256	1			T2	15		T4	358		T5	1
valid_sources[0x48]	365408	1			T2	9		T4	362		T7	42
valid_sources[0x49]	371384	1			T2	8		T4	362		T5	3
valid_sources[0x4a]	403262	1			T2	12		T4	346		T5	1
valid_sources[0x4b]	368188	1			T2	10		T4	352		T5	2
valid_sources[0x4c]	377314	1			T2	5		T4	349		T5	1
valid_sources[0x4d]	426644	1			T2	6		T4	363		T5	1
valid_sources[0x4e]	395890	1			T2	4		T4	351		T7	71
valid_sources[0x4f]	425718	1			T2	8		T4	404		T7	68
valid_sources[0x50]	357487	1			T2	7		T4	367		T5	2
valid_sources[0x51]	428081	1			T2	5		T4	322		T7	46
valid_sources[0x52]	379776	1			T2	16		T4	345		T5	2
valid_sources[0x53]	370178	1			T2	8		T4	365		T5	2
valid_sources[0x54]	366871	1			T2	4		T4	352		T5	1
valid_sources[0x55]	581791	1			T2	13		T4	375		T5	2
valid_sources[0x56]	373696	1			T2	7		T4	359		T7	34
valid_sources[0x57]	409336	1			T2	9		T4	358		T7	60
valid_sources[0x58]	357334	1			T2	4		T4	330		T7	39
valid_sources[0x59]	351801	1			T2	7		T4	355		T5	3
valid_sources[0x5a]	456473	1			T2	8		T4	313		T5	2
valid_sources[0x5b]	440348	1			T2	10		T4	337		T5	1
valid_sources[0x5c]	362506	1			T2	3		T4	372		T7	79
valid_sources[0x5d]	367525	1			T2	9		T4	355		T7	54
valid_sources[0x5e]	372989	1			T2	9		T4	363		T5	1
valid_sources[0x5f]	364579	1			T2	11		T4	378		T7	54
valid_sources[0x60]	394419	1			T2	12		T4	353		T7	47
valid_sources[0x61]	394395	1			T2	5		T4	369		T5	1
valid_sources[0x62]	372502	1			T2	1		T4	377		T5	2
valid_sources[0x63]	372803	1			T2	6		T4	360		T5	1
valid_sources[0x64]	461662	1			T2	5		T3	842		T4	369
valid_sources[0x65]	352115	1			T2	7		T4	366		T7	43
valid_sources[0x66]	372579	1			T2	5		T4	384		T5	1
valid_sources[0x67]	390989	1			T2	14		T4	361		T7	36
valid_sources[0x68]	399209	1			T2	8		T4	373		T7	61
valid_sources[0x69]	368705	1			T2	9		T4	343		T7	33
valid_sources[0x6a]	346680	1			T2	5		T4	361		T7	76
valid_sources[0x6b]	368127	1			T2	8		T4	369		T7	63
valid_sources[0x6c]	366182	1			T2	7		T4	378		T5	2
valid_sources[0x6d]	376707	1			T2	8		T4	345		T5	1
valid_sources[0x6e]	364548	1			T2	4		T4	350		T5	2
valid_sources[0x6f]	366675	1			T2	5		T4	359		T5	1
valid_sources[0x70]	372275	1			T2	8		T4	373		T5	2
valid_sources[0x71]	397307	1			T2	7		T4	372		T5	2
valid_sources[0x72]	367109	1			T2	8		T4	365		T7	55
valid_sources[0x73]	366711	1			T2	6		T4	367		T7	59
valid_sources[0x74]	372003	1			T2	4		T4	348		T7	45
valid_sources[0x75]	401618	1			T2	13		T4	340		T7	39
valid_sources[0x76]	418517	1			T2	4		T4	349		T5	2
valid_sources[0x77]	350509	1			T2	10		T4	362		T5	2
valid_sources[0x78]	376614	1			T2	6		T4	318		T7	46
valid_sources[0x79]	376987	1			T2	10		T4	375		T5	1
valid_sources[0x7a]	427444	1			T2	13		T4	384		T5	2
valid_sources[0x7b]	473369	1			T2	10		T4	349		T5	1
valid_sources[0x7c]	357831	1			T2	14		T4	340		T7	24
valid_sources[0x7d]	389920	1			T2	12		T4	384		T5	1
valid_sources[0x7e]	446384	1			T2	18		T4	364		T7	52
valid_sources[0x7f]	397177	1			T2	16		T4	335		T5	1
valid_sources[0x80]	356455	1			T2	9		T4	365		T5	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19320985

1

T1

5

T2

71

T3

279

values[0x0]

all_enables

biggest_size

4669728

1

T1

52

T2

78

T3

68

values[0x1]

all_enables

biggest_size

4612305

1

T1

41

T2

49

T3

35