Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	15331903	0	0
ctrl_rd_A	2147483647	290097	0	0
intr_enable_rd_A	2147483647	257920	0	0
ovrd_rd_A	2147483647	291158	0	0
timeout_ctrl_rd_A	2147483647	291341	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15331903	0	0
T12	560367	218369	0	0
T14	699295	0	0	0
T17	0	63733	0	0
T18	148497	0	0	0
T19	0	93169	0	0
T20	113992	0	0	0
T21	723884	0	0	0
T29	0	226838	0	0
T30	0	281930	0	0
T31	0	69446	0	0
T32	0	256889	0	0
T33	0	426000	0	0
T34	0	335475	0	0
T35	0	129004	0	0
T36	366612	0	0	0
T37	158114	0	0	0
T38	875247	0	0	0
T39	454763	0	0	0
T40	68401	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	290097	0	0
T29	964326	26765	0	0
T30	895266	0	0	0
T31	390983	7977	0	0
T32	635677	0	0	0
T33	117305	0	0	0
T34	0	18310	0	0
T47	72727	0	0	0
T48	19693	0	0	0
T52	0	12433	0	0
T58	0	10069	0	0
T102	0	18924	0	0
T103	0	15183	0	0
T104	0	6262	0	0
T105	0	5996	0	0
T106	0	6793	0	0
T107	49921	0	0	0
T108	75463	0	0	0
T109	317027	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	257920	0	0
T29	964326	23976	0	0
T30	895266	0	0	0
T31	390983	6728	0	0
T32	635677	0	0	0
T33	117305	0	0	0
T34	0	16079	0	0
T47	72727	0	0	0
T48	19693	0	0	0
T52	0	10655	0	0
T58	0	9283	0	0
T102	0	17281	0	0
T103	0	13747	0	0
T104	0	6015	0	0
T105	0	5412	0	0
T106	0	5724	0	0
T107	49921	0	0	0
T108	75463	0	0	0
T109	317027	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	291158	0	0
T29	964326	26329	0	0
T30	895266	0	0	0
T31	390983	7582	0	0
T32	635677	0	0	0
T33	117305	0	0	0
T34	0	17401	0	0
T47	72727	0	0	0
T48	19693	0	0	0
T52	0	12770	0	0
T58	0	9661	0	0
T102	0	19273	0	0
T103	0	14921	0	0
T104	0	6900	0	0
T105	0	5842	0	0
T106	0	6418	0	0
T107	49921	0	0	0
T108	75463	0	0	0
T109	317027	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	291341	0	0
T29	964326	25537	0	0
T30	895266	0	0	0
T31	390983	8152	0	0
T32	635677	0	0	0
T33	117305	0	0	0
T34	0	17725	0	0
T47	72727	0	0	0
T48	19693	0	0	0
T52	0	12506	0	0
T58	0	10170	0	0
T102	0	19099	0	0
T103	0	15808	0	0
T104	0	6708	0	0
T105	0	6245	0	0
T106	0	6778	0	0
T107	49921	0	0	0
T108	75463	0	0	0
T109	317027	0	0	0