Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	77056236	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

29837790

1

T1

636199

T2

110

T3

67

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	95514018	1			T1	118347		T2	142		T3	89
values[0x0]	5380128	1			T1	71356		T2	66		T3	52
values[0x1]	5999880	1			T1	80856		T2	74		T3	39

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	53213870	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

53680156

1

T1

812022

T2

151

T3

81

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	401162	1			T1	2542		T4	5		T7	70
valid_sources[0x01]	413859	1			T1	8810		T4	5		T7	8
valid_sources[0x02]	449466	1			T1	4665		T4	10		T7	43
valid_sources[0x03]	438491	1			T1	5114		T2	17		T4	3
valid_sources[0x04]	415792	1			T1	2276		T4	3		T7	14
valid_sources[0x05]	411882	1			T1	1641		T4	3		T7	24
valid_sources[0x06]	378957	1			T1	6000		T4	4		T7	27
valid_sources[0x07]	422923	1			T1	5852		T4	15		T7	51
valid_sources[0x08]	397407	1			T1	11317		T4	14		T7	61
valid_sources[0x09]	382839	1			T1	6666		T4	10		T7	19
valid_sources[0x0a]	420216	1			T1	7108		T4	2		T7	19
valid_sources[0x0b]	431943	1			T1	2394		T4	7		T7	41
valid_sources[0x0c]	432052	1			T1	2773		T4	16		T7	37
valid_sources[0x0d]	377358	1			T1	3360		T4	8		T7	8
valid_sources[0x0e]	415736	1			T1	2110		T4	9		T7	26
valid_sources[0x0f]	422026	1			T1	4265		T4	7		T7	12
valid_sources[0x10]	391197	1			T1	1842		T4	7		T7	12
valid_sources[0x11]	418122	1			T1	9084		T4	4		T7	43
valid_sources[0x12]	405250	1			T1	698		T4	5		T7	26
valid_sources[0x13]	435998	1			T1	7349		T4	6		T5	2
valid_sources[0x14]	426006	1			T1	4220		T4	9		T7	17
valid_sources[0x15]	482560	1			T1	3681		T4	5		T7	16
valid_sources[0x16]	399073	1			T1	6674		T4	6		T7	19
valid_sources[0x17]	380214	1			T1	6336		T4	6		T5	1
valid_sources[0x18]	393527	1			T1	1103		T4	2		T7	37
valid_sources[0x19]	403196	1			T1	4481		T4	6		T7	42
valid_sources[0x1a]	428644	1			T1	3015		T4	4		T7	91
valid_sources[0x1b]	404661	1			T1	6530		T4	4		T7	34
valid_sources[0x1c]	388532	1			T1	6159		T4	5		T7	35
valid_sources[0x1d]	455413	1			T1	4350		T4	8		T7	8
valid_sources[0x1e]	415325	1			T1	10080		T4	7		T7	45
valid_sources[0x1f]	439127	1			T1	7470		T4	14		T7	27
valid_sources[0x20]	414119	1			T1	3262		T4	9		T7	14
valid_sources[0x21]	443003	1			T1	3519		T4	3		T7	41
valid_sources[0x22]	420030	1			T1	4467		T2	262		T4	8
valid_sources[0x23]	407448	1			T1	4645		T4	1		T7	19
valid_sources[0x24]	401072	1			T1	4503		T4	6		T7	3
valid_sources[0x25]	374723	1			T1	1805		T4	11		T5	5
valid_sources[0x26]	462683	1			T1	3092		T4	8		T7	23
valid_sources[0x27]	429306	1			T1	10261		T4	2		T7	20
valid_sources[0x28]	378247	1			T1	1632		T4	4		T7	20
valid_sources[0x29]	392551	1			T1	5636		T4	5		T7	44
valid_sources[0x2a]	386256	1			T1	4655		T4	6		T7	16
valid_sources[0x2b]	416051	1			T1	3243		T4	2		T7	8
valid_sources[0x2c]	424672	1			T1	13120		T4	1		T7	4
valid_sources[0x2d]	513515	1			T1	7696		T4	3		T7	13
valid_sources[0x2e]	406303	1			T1	9521		T4	9		T7	12
valid_sources[0x2f]	404401	1			T1	3471		T4	5		T7	52
valid_sources[0x30]	426996	1			T1	2246		T4	8		T7	27
valid_sources[0x31]	432245	1			T1	3619		T4	3		T7	67
valid_sources[0x32]	418506	1			T1	3306		T4	8		T7	13
valid_sources[0x33]	415521	1			T1	3498		T4	5		T5	3
valid_sources[0x34]	482648	1			T1	5154		T4	3		T7	47
valid_sources[0x35]	401335	1			T1	3989		T4	6		T7	44
valid_sources[0x36]	413647	1			T1	6106		T4	4		T7	44
valid_sources[0x37]	400184	1			T1	7989		T4	7		T7	44
valid_sources[0x38]	420150	1			T1	6383		T4	5		T7	15
valid_sources[0x39]	396278	1			T1	5196		T4	3		T7	16
valid_sources[0x3a]	414428	1			T1	9721		T4	4		T7	40
valid_sources[0x3b]	401683	1			T1	2063		T4	12		T7	8
valid_sources[0x3c]	400990	1			T1	1921		T4	13		T5	1
valid_sources[0x3d]	410828	1			T1	8626		T4	5		T5	2
valid_sources[0x3e]	396813	1			T1	6476		T4	8		T7	29
valid_sources[0x3f]	406256	1			T1	5730		T4	11		T7	61
valid_sources[0x40]	385864	1			T1	6150		T4	4		T7	15
valid_sources[0x41]	386420	1			T1	3350		T4	6		T7	19
valid_sources[0x42]	448177	1			T1	6505		T4	1		T7	9
valid_sources[0x43]	435201	1			T1	2617		T4	12		T7	63
valid_sources[0x44]	445985	1			T1	2976		T4	10		T7	23
valid_sources[0x45]	455459	1			T1	2910		T4	4		T7	91
valid_sources[0x46]	450770	1			T1	7447		T4	4		T7	18
valid_sources[0x47]	379899	1			T1	4954		T4	10		T7	24
valid_sources[0x48]	402427	1			T1	9219		T4	6		T7	30
valid_sources[0x49]	583710	1			T1	10911		T4	2		T7	49
valid_sources[0x4a]	383442	1			T1	5322		T4	3		T7	40
valid_sources[0x4b]	407313	1			T1	5051		T4	10		T7	19
valid_sources[0x4c]	422856	1			T1	969		T4	17		T7	17
valid_sources[0x4d]	405854	1			T1	3041		T4	7		T7	19
valid_sources[0x4e]	397372	1			T1	5981		T4	9		T7	21
valid_sources[0x4f]	455148	1			T1	25229		T2	1		T4	6
valid_sources[0x50]	427180	1			T1	8564		T4	6		T7	13
valid_sources[0x51]	392033	1			T1	6126		T4	6		T7	23
valid_sources[0x52]	381975	1			T1	878		T5	1		T7	61
valid_sources[0x53]	412957	1			T1	9517		T4	12		T7	36
valid_sources[0x54]	402714	1			T1	7959		T4	11		T7	35
valid_sources[0x55]	400787	1			T1	3612		T4	6		T7	47
valid_sources[0x56]	469367	1			T1	7219		T4	8		T7	3
valid_sources[0x57]	406742	1			T1	2875		T3	180		T7	23
valid_sources[0x58]	420112	1			T1	4067		T4	9		T7	5
valid_sources[0x59]	416114	1			T1	9809		T4	6		T7	24
valid_sources[0x5a]	405927	1			T1	5437		T4	7		T7	35
valid_sources[0x5b]	425871	1			T1	9598		T4	2		T7	25
valid_sources[0x5c]	391482	1			T1	7673		T4	11		T7	81
valid_sources[0x5d]	408350	1			T1	5502		T4	9		T7	11
valid_sources[0x5e]	406137	1			T1	7914		T4	5		T7	39
valid_sources[0x5f]	402179	1			T1	6502		T4	6		T7	32
valid_sources[0x60]	415301	1			T1	8142		T4	6		T7	30
valid_sources[0x61]	451698	1			T1	2690		T4	3		T7	15
valid_sources[0x62]	389624	1			T1	4410		T4	2		T7	9
valid_sources[0x63]	483947	1			T1	4688		T4	2		T7	12
valid_sources[0x64]	513086	1			T1	4690		T2	1		T4	4
valid_sources[0x65]	401804	1			T1	2136		T4	4		T7	39
valid_sources[0x66]	395348	1			T1	8532		T4	11		T7	24
valid_sources[0x67]	422405	1			T1	6163		T4	7		T7	37
valid_sources[0x68]	399379	1			T1	1102		T4	4		T7	32
valid_sources[0x69]	439202	1			T1	4830		T4	3		T7	35
valid_sources[0x6a]	430611	1			T1	1454		T4	9		T7	12
valid_sources[0x6b]	431352	1			T1	3481		T4	12		T7	44
valid_sources[0x6c]	419294	1			T1	4457		T4	5		T7	51
valid_sources[0x6d]	380490	1			T1	3169		T4	14		T7	12
valid_sources[0x6e]	383129	1			T1	3751		T4	5		T5	6
valid_sources[0x6f]	398637	1			T1	9328		T4	2		T7	15
valid_sources[0x70]	416227	1			T1	2201		T4	9		T7	16
valid_sources[0x71]	389287	1			T1	2755		T5	1		T7	14
valid_sources[0x72]	382129	1			T1	2510		T4	8		T7	4
valid_sources[0x73]	391909	1			T1	8085		T4	10		T5	1
valid_sources[0x74]	642494	1			T1	6321		T4	8		T7	55
valid_sources[0x75]	439882	1			T1	2241		T4	9		T7	62
valid_sources[0x76]	505346	1			T1	1495		T4	9		T7	12
valid_sources[0x77]	431840	1			T1	1319		T4	2		T7	49
valid_sources[0x78]	414562	1			T1	7788		T4	11		T7	33
valid_sources[0x79]	410279	1			T1	9567		T4	8		T7	20
valid_sources[0x7a]	423269	1			T1	4947		T4	4		T7	36
valid_sources[0x7b]	407657	1			T1	3466		T4	3		T7	11
valid_sources[0x7c]	392652	1			T1	5125		T4	2		T7	36
valid_sources[0x7d]	438436	1			T1	6960		T4	10		T7	30
valid_sources[0x7e]	441657	1			T1	8790		T4	9		T7	60
valid_sources[0x7f]	388646	1			T1	3301		T4	5		T7	41
valid_sources[0x80]	406493	1			T1	6689		T4	12		T5	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19681256

1

T1

496800

T2

67

T3

37

values[0x0]

all_enables

biggest_size

5108409

1

T1

69592

T2

28

T3

19

values[0x1]

all_enables

biggest_size

5048125

1

T1

69807

T2

15

T3

11