Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	16669956	0	0
ctrl_rd_A	2147483647	352475	0	0
intr_enable_rd_A	2147483647	308402	0	0
ovrd_rd_A	2147483647	351135	0	0
timeout_ctrl_rd_A	2147483647	348752	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16669956	0	0
T1	628595	237954	0	0
T2	198975	0	0	0
T3	130527	0	0	0
T4	172640	0	0	0
T5	48199	0	0	0
T6	194795	0	0	0
T7	135118	0	0	0
T8	983193	0	0	0
T9	158877	0	0	0
T10	768784	0	0	0
T12	0	300932	0	0
T17	0	350711	0	0
T18	0	154586	0	0
T27	0	264726	0	0
T28	0	104314	0	0
T29	0	102821	0	0
T30	0	164840	0	0
T31	0	48220	0	0
T32	0	100898	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	352475	0	0
T12	905882	11306	0	0
T20	234130	0	0	0
T22	1196	0	0	0
T32	0	10965	0	0
T34	970045	0	0	0
T35	717158	0	0	0
T56	0	23606	0	0
T57	0	12334	0	0
T58	0	11783	0	0
T117	0	3501	0	0
T118	0	10444	0	0
T119	0	12782	0	0
T120	0	40747	0	0
T121	0	7201	0	0
T122	238908	0	0	0
T123	627052	0	0	0
T124	908774	0	0	0
T125	113592	0	0	0
T126	170096	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	308402	0	0
T12	905882	10189	0	0
T20	234130	0	0	0
T22	1196	0	0	0
T32	0	9697	0	0
T34	970045	0	0	0
T35	717158	0	0	0
T56	0	21156	0	0
T57	0	10454	0	0
T58	0	10787	0	0
T117	0	2920	0	0
T118	0	8995	0	0
T119	0	11410	0	0
T120	0	36018	0	0
T122	238908	0	0	0
T123	627052	0	0	0
T124	908774	0	0	0
T125	113592	0	0	0
T126	170096	0	0	0
T127	0	21	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	351135	0	0
T12	905882	11462	0	0
T20	234130	0	0	0
T22	1196	0	0	0
T32	0	10938	0	0
T34	970045	0	0	0
T35	717158	0	0	0
T56	0	23761	0	0
T57	0	12029	0	0
T58	0	12243	0	0
T117	0	3142	0	0
T118	0	10603	0	0
T119	0	12608	0	0
T120	0	42086	0	0
T121	0	6981	0	0
T122	238908	0	0	0
T123	627052	0	0	0
T124	908774	0	0	0
T125	113592	0	0	0
T126	170096	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	348752	0	0
T12	905882	11045	0	0
T20	234130	0	0	0
T22	1196	0	0	0
T32	0	11084	0	0
T34	970045	0	0	0
T35	717158	0	0	0
T56	0	23527	0	0
T57	0	12043	0	0
T58	0	12507	0	0
T117	0	3243	0	0
T118	0	10702	0	0
T119	0	12934	0	0
T120	0	40967	0	0
T121	0	6890	0	0
T122	238908	0	0	0
T123	627052	0	0	0
T124	908774	0	0	0
T125	113592	0	0	0
T126	170096	0	0	0