Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	15092775	0	0
ctrl_rd_A	2147483647	271526	0	0
intr_enable_rd_A	2147483647	238110	0	0
ovrd_rd_A	2147483647	268722	0	0
timeout_ctrl_rd_A	2147483647	267954	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15092775	0	0
T9	266074	76667	0	0
T10	190826	0	0	0
T11	180254	0	0	0
T12	218795	0	0	0
T13	0	56729	0	0
T14	42177	0	0	0
T18	0	158072	0	0
T19	0	212313	0	0
T22	121885	0	0	0
T23	0	19559	0	0
T29	0	74734	0	0
T30	0	147522	0	0
T31	0	45388	0	0
T32	0	128034	0	0
T33	0	48499	0	0
T34	230144	0	0	0
T35	163231	0	0	0
T36	410670	0	0	0
T37	184708	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	271526	0	0
T9	266074	5217	0	0
T10	190826	0	0	0
T11	180254	0	0	0
T12	218795	0	0	0
T14	42177	0	0	0
T18	0	6984	0	0
T22	121885	0	0	0
T29	0	8753	0	0
T34	230144	0	0	0
T35	163231	0	0	0
T36	410670	0	0	0
T37	184708	0	0	0
T97	0	10272	0	0
T98	0	4789	0	0
T99	0	7793	0	0
T100	0	3144	0	0
T101	0	12510	0	0
T102	0	15602	0	0
T103	0	3828	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	238110	0	0
T7	100076	58	0	0
T8	830978	0	0	0
T9	266074	4587	0	0
T10	190826	0	0	0
T11	180254	0	0	0
T12	218795	0	0	0
T14	42177	0	0	0
T18	0	6114	0	0
T22	121885	0	0	0
T29	0	7228	0	0
T34	230144	0	0	0
T35	163231	0	0	0
T97	0	9056	0	0
T98	0	3978	0	0
T99	0	6878	0	0
T100	0	2660	0	0
T101	0	11379	0	0
T104	0	23	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	268722	0	0
T9	266074	5125	0	0
T10	190826	0	0	0
T11	180254	0	0	0
T12	218795	0	0	0
T14	42177	0	0	0
T18	0	7138	0	0
T22	121885	0	0	0
T29	0	8498	0	0
T34	230144	0	0	0
T35	163231	0	0	0
T36	410670	0	0	0
T37	184708	0	0	0
T97	0	10294	0	0
T98	0	4812	0	0
T99	0	7664	0	0
T100	0	3192	0	0
T101	0	12715	0	0
T102	0	14950	0	0
T103	0	3700	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	267954	0	0
T9	266074	5126	0	0
T10	190826	0	0	0
T11	180254	0	0	0
T12	218795	0	0	0
T14	42177	0	0	0
T18	0	7476	0	0
T22	121885	0	0	0
T29	0	8701	0	0
T34	230144	0	0	0
T35	163231	0	0	0
T36	410670	0	0	0
T37	184708	0	0	0
T97	0	9792	0	0
T98	0	4668	0	0
T99	0	7454	0	0
T100	0	3253	0	0
T101	0	12156	0	0
T102	0	15103	0	0
T103	0	4129	0	0