Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	80147813	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

29459733

1

T1

86

T2

188

T3

87

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	98127966	1			T1	220		T2	11146		T3	73
values[0x0]	5426385	1			T1	112		T2	75		T3	85
values[0x1]	6053195	1			T1	132		T2	81		T3	88

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55180819	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

54426727

1

T1

182

T2

3880

T3

111

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	408402	1			T2	41		T3	2		T5	61
valid_sources[0x01]	418490	1			T2	48		T5	56		T7	1803
valid_sources[0x02]	495337	1			T1	3		T2	43		T4	11
valid_sources[0x03]	406546	1			T1	2		T2	45		T3	4
valid_sources[0x04]	420272	1			T1	2		T2	64		T4	34
valid_sources[0x05]	440065	1			T1	1		T2	38		T3	2
valid_sources[0x06]	412330	1			T1	1		T2	40		T4	8
valid_sources[0x07]	439452	1			T1	2		T2	49		T4	75
valid_sources[0x08]	403818	1			T1	2		T2	48		T4	56
valid_sources[0x09]	402581	1			T1	2		T2	37		T3	2
valid_sources[0x0a]	422604	1			T1	1		T2	56		T5	60
valid_sources[0x0b]	423548	1			T2	58		T4	9		T5	58
valid_sources[0x0c]	401082	1			T1	1		T2	45		T3	2
valid_sources[0x0d]	409961	1			T1	2		T2	45		T3	1
valid_sources[0x0e]	524612	1			T1	8		T2	41		T5	62
valid_sources[0x0f]	410445	1			T1	1		T2	48		T4	18
valid_sources[0x10]	467864	1			T1	1		T2	39		T4	46
valid_sources[0x11]	468178	1			T1	4		T2	50		T3	3
valid_sources[0x12]	502913	1			T1	5		T2	39		T3	7
valid_sources[0x13]	446473	1			T1	1		T2	48		T4	116
valid_sources[0x14]	405906	1			T1	2		T2	44		T3	5
valid_sources[0x15]	420032	1			T1	2		T2	52		T3	1
valid_sources[0x16]	412996	1			T1	1		T2	43		T4	5
valid_sources[0x17]	408972	1			T1	1		T2	47		T5	63
valid_sources[0x18]	403843	1			T1	3		T2	48		T4	14
valid_sources[0x19]	407327	1			T1	3		T2	49		T3	1
valid_sources[0x1a]	418474	1			T1	3		T2	50		T3	1
valid_sources[0x1b]	432996	1			T1	2		T2	50		T4	1
valid_sources[0x1c]	393374	1			T1	1		T2	52		T3	2
valid_sources[0x1d]	402871	1			T1	2		T2	42		T5	45
valid_sources[0x1e]	425676	1			T1	1		T2	46		T3	1
valid_sources[0x1f]	387105	1			T1	2		T2	55		T4	42
valid_sources[0x20]	394180	1			T1	2		T2	34		T4	26
valid_sources[0x21]	465279	1			T1	1		T2	42		T4	29
valid_sources[0x22]	411241	1			T1	1		T2	46		T5	52
valid_sources[0x23]	407198	1			T1	3		T2	55		T3	4
valid_sources[0x24]	520173	1			T1	1		T2	48		T5	53
valid_sources[0x25]	414082	1			T1	2		T2	39		T4	26
valid_sources[0x26]	413381	1			T2	34		T3	1		T5	75
valid_sources[0x27]	389859	1			T1	1		T2	27		T3	2
valid_sources[0x28]	403132	1			T2	44		T4	24		T5	58
valid_sources[0x29]	409270	1			T1	1		T2	49		T5	58
valid_sources[0x2a]	458297	1			T1	3		T2	41		T5	41
valid_sources[0x2b]	407909	1			T1	2		T2	65		T3	1
valid_sources[0x2c]	448160	1			T1	2		T2	47		T3	1
valid_sources[0x2d]	436265	1			T1	2		T2	45		T3	2
valid_sources[0x2e]	405280	1			T1	1		T2	37		T4	27
valid_sources[0x2f]	386898	1			T1	4		T2	52		T3	1
valid_sources[0x30]	426054	1			T1	1		T2	39		T3	1
valid_sources[0x31]	398231	1			T2	58		T3	3		T5	47
valid_sources[0x32]	535834	1			T1	1		T2	41		T4	31
valid_sources[0x33]	443435	1			T1	1		T2	42		T3	1
valid_sources[0x34]	462704	1			T1	1		T2	58		T3	1
valid_sources[0x35]	424369	1			T1	2		T2	44		T3	3
valid_sources[0x36]	400503	1			T2	41		T3	1		T5	53
valid_sources[0x37]	423273	1			T1	1		T2	42		T4	174
valid_sources[0x38]	415788	1			T1	5		T2	44		T3	5
valid_sources[0x39]	490187	1			T1	2		T2	45		T3	1
valid_sources[0x3a]	406869	1			T1	2		T2	56		T5	45
valid_sources[0x3b]	407117	1			T1	3		T2	42		T3	2
valid_sources[0x3c]	445230	1			T2	42		T4	13		T5	58
valid_sources[0x3d]	424101	1			T1	4		T2	38		T5	36
valid_sources[0x3e]	392367	1			T1	1		T2	40		T3	1
valid_sources[0x3f]	399669	1			T1	4		T2	51		T3	1
valid_sources[0x40]	397848	1			T1	2		T2	46		T4	18
valid_sources[0x41]	404378	1			T1	8		T2	45		T5	60
valid_sources[0x42]	421957	1			T1	1		T2	45		T3	1
valid_sources[0x43]	422995	1			T1	2		T2	55		T4	5
valid_sources[0x44]	412757	1			T1	3		T2	51		T3	2
valid_sources[0x45]	390720	1			T1	1		T2	50		T3	7
valid_sources[0x46]	452233	1			T2	41		T4	48		T5	43
valid_sources[0x47]	434791	1			T1	5		T2	37		T4	5
valid_sources[0x48]	406165	1			T2	39		T4	41		T5	59
valid_sources[0x49]	454890	1			T1	1		T2	49		T4	16
valid_sources[0x4a]	406412	1			T1	5		T2	46		T4	18
valid_sources[0x4b]	457835	1			T2	49		T3	2		T5	65
valid_sources[0x4c]	432362	1			T1	3		T2	42		T3	1
valid_sources[0x4d]	488461	1			T1	2		T2	53		T5	57
valid_sources[0x4e]	404798	1			T2	48		T5	57		T6	2
valid_sources[0x4f]	403265	1			T1	1		T2	43		T3	2
valid_sources[0x50]	430450	1			T1	1		T2	44		T3	2
valid_sources[0x51]	399090	1			T2	31		T3	2		T4	5
valid_sources[0x52]	418635	1			T1	2		T2	39		T4	2
valid_sources[0x53]	419703	1			T1	1		T2	29		T3	1
valid_sources[0x54]	494562	1			T1	1		T2	53		T3	2
valid_sources[0x55]	595517	1			T1	1		T2	41		T3	1
valid_sources[0x56]	402236	1			T1	4		T2	41		T4	5
valid_sources[0x57]	479973	1			T1	2		T2	29		T5	65
valid_sources[0x58]	446886	1			T1	1		T2	54		T3	3
valid_sources[0x59]	412107	1			T1	2		T2	53		T5	54
valid_sources[0x5a]	388997	1			T1	5		T2	46		T4	1
valid_sources[0x5b]	417024	1			T1	1		T2	49		T3	1
valid_sources[0x5c]	410402	1			T1	5		T2	45		T5	58
valid_sources[0x5d]	471189	1			T1	3		T2	55		T3	3
valid_sources[0x5e]	419766	1			T1	1		T2	50		T3	1
valid_sources[0x5f]	523942	1			T1	1		T2	47		T3	2
valid_sources[0x60]	416859	1			T1	5		T2	54		T3	1
valid_sources[0x61]	422664	1			T1	1		T2	41		T3	4
valid_sources[0x62]	399117	1			T1	3		T2	45		T3	1
valid_sources[0x63]	493908	1			T2	39		T3	2		T5	52
valid_sources[0x64]	497879	1			T1	2		T2	43		T5	60
valid_sources[0x65]	408793	1			T1	2		T2	47		T3	2
valid_sources[0x66]	404121	1			T1	1		T2	48		T3	1
valid_sources[0x67]	402638	1			T1	3		T2	38		T3	1
valid_sources[0x68]	431044	1			T2	47		T3	1		T5	46
valid_sources[0x69]	392854	1			T1	1		T2	41		T3	2
valid_sources[0x6a]	422178	1			T1	1		T2	49		T3	1
valid_sources[0x6b]	414060	1			T1	2		T2	41		T3	1
valid_sources[0x6c]	419539	1			T1	1		T2	38		T3	1
valid_sources[0x6d]	390760	1			T1	2		T2	34		T3	1
valid_sources[0x6e]	435036	1			T2	42		T3	2		T4	32
valid_sources[0x6f]	454964	1			T1	2		T2	33		T5	65
valid_sources[0x70]	406536	1			T1	1		T2	33		T4	8
valid_sources[0x71]	427516	1			T1	5		T2	61		T4	19
valid_sources[0x72]	417216	1			T1	2		T2	48		T3	1
valid_sources[0x73]	410327	1			T2	54		T4	71		T5	44
valid_sources[0x74]	409467	1			T1	2		T2	46		T4	37
valid_sources[0x75]	393534	1			T1	2		T2	35		T5	55
valid_sources[0x76]	441159	1			T1	2		T2	55		T5	43
valid_sources[0x77]	457170	1			T2	44		T3	3		T5	57
valid_sources[0x78]	401714	1			T1	1		T2	39		T3	1
valid_sources[0x79]	410993	1			T1	4		T2	35		T4	50
valid_sources[0x7a]	420077	1			T1	4		T2	35		T3	2
valid_sources[0x7b]	403732	1			T1	1		T2	32		T5	59
valid_sources[0x7c]	464256	1			T1	2		T2	45		T4	1
valid_sources[0x7d]	429014	1			T2	42		T4	16		T5	51
valid_sources[0x7e]	423838	1			T1	1		T2	41		T4	2
valid_sources[0x7f]	452323	1			T1	2		T2	37		T3	1
valid_sources[0x80]	446052	1			T2	50		T5	56		T7	1741

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19251745

1

T1

13

T2

129

T3

31

values[0x0]

all_enables

biggest_size

5138355

1

T1

49

T2

36

T3

38

values[0x1]

all_enables

biggest_size

5069633

1

T1

24

T2

23

T3

18