Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	16870763	0	0
ctrl_rd_A	2147483647	279366	0	0
intr_enable_rd_A	2147483647	246143	0	0
ovrd_rd_A	2147483647	276967	0	0
timeout_ctrl_rd_A	2147483647	276618	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16870763	0	0
T7	102723	224817	0	0
T8	104953	0	0	0
T9	203763	0	0	0
T10	811581	0	0	0
T12	0	14502	0	0
T13	253233	0	0	0
T20	0	66505	0	0
T31	16368	0	0	0
T32	0	112851	0	0
T33	0	414513	0	0
T34	0	76626	0	0
T35	0	111594	0	0
T36	0	66878	0	0
T37	0	296552	0	0
T38	0	53677	0	0
T39	212573	0	0	0
T40	702642	0	0	0
T41	223991	0	0	0
T42	220283	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	279366	0	0
T7	102723	25770	0	0
T8	104953	0	0	0
T9	203763	0	0	0
T10	811581	0	0	0
T12	0	1808	0	0
T13	253233	0	0	0
T20	0	3581	0	0
T31	16368	0	0	0
T36	0	2915	0	0
T39	212573	0	0	0
T40	702642	0	0	0
T41	223991	0	0	0
T42	220283	0	0	0
T98	0	11601	0	0
T99	0	6761	0	0
T100	0	8586	0	0
T101	0	6618	0	0
T102	0	5913	0	0
T103	0	12955	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	246143	0	0
T7	102723	22404	0	0
T8	104953	0	0	0
T9	203763	0	0	0
T10	811581	0	0	0
T12	0	1514	0	0
T13	253233	0	0	0
T16	0	4	0	0
T20	0	3146	0	0
T31	16368	0	0	0
T36	0	2508	0	0
T39	212573	0	0	0
T40	702642	0	0	0
T41	223991	0	0	0
T42	220283	0	0	0
T71	0	24	0	0
T98	0	9711	0	0
T99	0	6005	0	0
T100	0	7398	0	0
T101	0	5615	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	276967	0	0
T7	102723	25136	0	0
T8	104953	0	0	0
T9	203763	0	0	0
T10	811581	0	0	0
T12	0	1729	0	0
T13	253233	0	0	0
T20	0	3543	0	0
T31	16368	0	0	0
T36	0	3060	0	0
T39	212573	0	0	0
T40	702642	0	0	0
T41	223991	0	0	0
T42	220283	0	0	0
T98	0	11398	0	0
T99	0	6811	0	0
T100	0	8421	0	0
T101	0	6807	0	0
T102	0	5757	0	0
T103	0	13054	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	276618	0	0
T7	102723	25103	0	0
T8	104953	0	0	0
T9	203763	0	0	0
T10	811581	0	0	0
T12	0	1811	0	0
T13	253233	0	0	0
T20	0	3391	0	0
T31	16368	0	0	0
T36	0	2872	0	0
T39	212573	0	0	0
T40	702642	0	0	0
T41	223991	0	0	0
T42	220283	0	0	0
T98	0	10857	0	0
T99	0	7553	0	0
T100	0	8341	0	0
T101	0	6595	0	0
T102	0	5730	0	0
T103	0	12822	0	0