Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14629901	0	0
ctrl_rd_A	2147483647	285111	0	0
intr_enable_rd_A	2147483647	253427	0	0
ovrd_rd_A	2147483647	282481	0	0
timeout_ctrl_rd_A	2147483647	283514	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14629901	0	0
T6	283557	73829	0	0
T7	656992	182768	0	0
T8	155320	0	0	0
T9	255401	0	0	0
T10	87286	0	0	0
T11	357638	0	0	0
T13	0	98357	0	0
T14	0	156847	0	0
T26	0	70912	0	0
T27	0	6455	0	0
T28	0	77840	0	0
T29	0	117971	0	0
T30	0	192023	0	0
T31	0	394856	0	0
T32	14907	0	0	0
T33	195806	0	0	0
T34	152019	0	0	0
T35	269659	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	285111	0	0
T6	283557	3109	0	0
T7	656992	0	0	0
T8	155320	0	0	0
T9	255401	0	0	0
T10	87286	0	0	0
T11	357638	0	0	0
T13	0	11450	0	0
T14	0	17658	0	0
T32	14907	0	0	0
T33	195806	0	0	0
T34	152019	0	0	0
T35	269659	0	0	0
T105	0	4445	0	0
T106	0	4166	0	0
T107	0	8115	0	0
T108	0	13221	0	0
T109	0	4572	0	0
T110	0	3858	0	0
T111	0	16943	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	253427	0	0
T6	283557	2827	0	0
T7	656992	0	0	0
T8	155320	0	0	0
T9	255401	0	0	0
T10	87286	0	0	0
T11	357638	0	0	0
T13	0	10259	0	0
T14	0	16031	0	0
T32	14907	0	0	0
T33	195806	0	0	0
T34	152019	0	0	0
T35	269659	0	0	0
T99	0	2	0	0
T105	0	3853	0	0
T106	0	3868	0	0
T107	0	7352	0	0
T108	0	12169	0	0
T109	0	4312	0	0
T110	0	3466	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	282481	0	0
T6	283557	3341	0	0
T7	656992	0	0	0
T8	155320	0	0	0
T9	255401	0	0	0
T10	87286	0	0	0
T11	357638	0	0	0
T13	0	10888	0	0
T14	0	17994	0	0
T32	14907	0	0	0
T33	195806	0	0	0
T34	152019	0	0	0
T35	269659	0	0	0
T105	0	4163	0	0
T106	0	4125	0	0
T107	0	8288	0	0
T108	0	12811	0	0
T109	0	4812	0	0
T110	0	3663	0	0
T111	0	16894	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	283514	0	0
T6	283557	3173	0	0
T7	656992	0	0	0
T8	155320	0	0	0
T9	255401	0	0	0
T10	87286	0	0	0
T11	357638	0	0	0
T13	0	11508	0	0
T14	0	18665	0	0
T32	14907	0	0	0
T33	195806	0	0	0
T34	152019	0	0	0
T35	269659	0	0	0
T105	0	4102	0	0
T106	0	4277	0	0
T107	0	7821	0	0
T108	0	13840	0	0
T109	0	4574	0	0
T110	0	3812	0	0
T111	0	17111	0	0