Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	74805725	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

30488974

1

T1

157

T2

4

T3

382

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	94681298	1			T1	2757		T2	1		T3	19142
values[0x0]	5017804	1			T1	171		T2	5		T3	304
values[0x1]	5595597	1			T1	158		T2	4		T3	311

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51907900	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

53386799

1

T1

1079

T2

5

T3

6881

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	412891	1			T1	8		T3	78		T4	2
valid_sources[0x01]	459722	1			T1	12		T3	75		T4	9
valid_sources[0x02]	389016	1			T1	12		T3	94		T4	1
valid_sources[0x03]	386853	1			T1	6		T3	81		T4	6
valid_sources[0x04]	410149	1			T1	22		T3	81		T4	2
valid_sources[0x05]	421686	1			T1	14		T3	84		T4	6
valid_sources[0x06]	440353	1			T1	4		T3	83		T4	5
valid_sources[0x07]	424266	1			T1	2		T3	77		T4	3
valid_sources[0x08]	425164	1			T1	7		T3	55		T4	4
valid_sources[0x09]	398831	1			T1	18		T3	63		T6	3487
valid_sources[0x0a]	382064	1			T1	2		T3	71		T4	4
valid_sources[0x0b]	394519	1			T1	33		T3	102		T4	4
valid_sources[0x0c]	477372	1			T1	8		T3	69		T4	9
valid_sources[0x0d]	396454	1			T1	31		T3	66		T4	6
valid_sources[0x0e]	401511	1			T1	7		T3	83		T4	1
valid_sources[0x0f]	416799	1			T1	11		T3	73		T4	8
valid_sources[0x10]	387180	1			T1	18		T3	60		T4	1
valid_sources[0x11]	393590	1			T1	16		T3	67		T4	5
valid_sources[0x12]	425473	1			T1	28		T3	62		T4	1
valid_sources[0x13]	477397	1			T1	12		T3	70		T4	5
valid_sources[0x14]	419035	1			T1	17		T3	89		T6	5592
valid_sources[0x15]	400561	1			T1	6		T3	82		T4	2
valid_sources[0x16]	403535	1			T1	21		T3	86		T6	3843
valid_sources[0x17]	397419	1			T1	5		T3	62		T4	5
valid_sources[0x18]	426891	1			T1	9		T3	64		T4	5
valid_sources[0x19]	426640	1			T1	6		T3	58		T4	4
valid_sources[0x1a]	387805	1			T1	2		T3	76		T4	4
valid_sources[0x1b]	430551	1			T1	5		T3	83		T4	1
valid_sources[0x1c]	412172	1			T1	10		T3	73		T4	4
valid_sources[0x1d]	410564	1			T1	9		T3	79		T4	2
valid_sources[0x1e]	414463	1			T1	20		T3	86		T4	1
valid_sources[0x1f]	387106	1			T1	34		T3	72		T4	8
valid_sources[0x20]	382812	1			T1	8		T3	65		T6	1645
valid_sources[0x21]	397126	1			T1	13		T3	82		T4	6
valid_sources[0x22]	408380	1			T3	70		T4	1		T6	541
valid_sources[0x23]	384999	1			T1	20		T3	84		T4	4
valid_sources[0x24]	404680	1			T1	23		T3	88		T4	3
valid_sources[0x25]	381810	1			T1	14		T3	57		T4	3
valid_sources[0x26]	386214	1			T1	10		T3	89		T6	2591
valid_sources[0x27]	397113	1			T1	11		T3	110		T4	1
valid_sources[0x28]	386367	1			T1	18		T3	70		T4	5
valid_sources[0x29]	395491	1			T1	13		T3	61		T6	545
valid_sources[0x2a]	403683	1			T1	7		T3	54		T4	1
valid_sources[0x2b]	394407	1			T1	21		T3	81		T4	3
valid_sources[0x2c]	387401	1			T1	7		T3	70		T4	12
valid_sources[0x2d]	378777	1			T1	18		T3	62		T4	7
valid_sources[0x2e]	437678	1			T1	16		T3	69		T4	1
valid_sources[0x2f]	429690	1			T1	20		T3	105		T4	10
valid_sources[0x30]	388777	1			T1	5		T3	68		T4	3
valid_sources[0x31]	399977	1			T1	22		T3	78		T4	9
valid_sources[0x32]	413617	1			T1	9		T3	69		T4	4
valid_sources[0x33]	411641	1			T1	8		T3	82		T6	2861
valid_sources[0x34]	394966	1			T1	36		T3	84		T4	4
valid_sources[0x35]	384736	1			T1	15		T3	76		T4	3
valid_sources[0x36]	483969	1			T1	13		T3	85		T6	1665
valid_sources[0x37]	386521	1			T1	19		T3	68		T6	372
valid_sources[0x38]	393952	1			T1	5		T3	75		T6	436
valid_sources[0x39]	383155	1			T1	20		T3	70		T4	1
valid_sources[0x3a]	397225	1			T1	14		T3	68		T6	1383
valid_sources[0x3b]	422429	1			T1	7		T3	71		T6	1626
valid_sources[0x3c]	455247	1			T1	4		T3	94		T4	4
valid_sources[0x3d]	408246	1			T1	9		T3	80		T4	1
valid_sources[0x3e]	402659	1			T1	18		T3	72		T4	4
valid_sources[0x3f]	390382	1			T1	19		T3	72		T4	4
valid_sources[0x40]	403836	1			T1	23		T3	71		T4	1
valid_sources[0x41]	450642	1			T1	21		T3	69		T6	5036
valid_sources[0x42]	385838	1			T1	3		T3	62		T6	686
valid_sources[0x43]	423085	1			T1	10		T3	83		T4	2
valid_sources[0x44]	414945	1			T1	5		T3	67		T4	3
valid_sources[0x45]	418300	1			T1	19		T3	81		T4	7
valid_sources[0x46]	455886	1			T1	11		T3	85		T4	2
valid_sources[0x47]	391202	1			T1	20		T2	2		T3	72
valid_sources[0x48]	476091	1			T1	2		T3	100		T6	2164
valid_sources[0x49]	378299	1			T1	4		T3	74		T4	2
valid_sources[0x4a]	384471	1			T1	11		T3	70		T4	1
valid_sources[0x4b]	391370	1			T1	21		T3	73		T4	3
valid_sources[0x4c]	385887	1			T1	15		T3	101		T4	10
valid_sources[0x4d]	450230	1			T1	17		T3	91		T4	6
valid_sources[0x4e]	403653	1			T1	6		T3	75		T4	5
valid_sources[0x4f]	418478	1			T1	10		T3	79		T6	4190
valid_sources[0x50]	465693	1			T1	23		T3	81		T4	1
valid_sources[0x51]	436168	1			T1	13		T3	76		T4	4
valid_sources[0x52]	399111	1			T1	6		T3	63		T4	4
valid_sources[0x53]	402196	1			T1	6		T3	73		T6	4430
valid_sources[0x54]	372717	1			T1	14		T3	78		T6	4104
valid_sources[0x55]	395682	1			T1	12		T3	55		T6	503
valid_sources[0x56]	405417	1			T1	11		T3	76		T4	4
valid_sources[0x57]	425107	1			T1	7		T3	82		T4	1
valid_sources[0x58]	473154	1			T1	18		T3	61		T6	626
valid_sources[0x59]	422772	1			T1	8		T3	65		T6	131
valid_sources[0x5a]	387230	1			T1	3		T3	75		T4	4
valid_sources[0x5b]	394989	1			T1	12		T3	75		T4	6
valid_sources[0x5c]	400610	1			T1	7		T3	83		T4	9
valid_sources[0x5d]	391251	1			T1	8		T3	68		T4	1
valid_sources[0x5e]	417362	1			T1	37		T3	96		T4	10
valid_sources[0x5f]	371712	1			T1	3		T3	68		T4	3
valid_sources[0x60]	391455	1			T1	23		T3	75		T4	4
valid_sources[0x61]	396386	1			T1	4		T3	100		T4	4
valid_sources[0x62]	441980	1			T1	16		T3	50		T4	2
valid_sources[0x63]	441553	1			T1	8		T3	69		T4	1
valid_sources[0x64]	591884	1			T1	9		T3	70		T4	3
valid_sources[0x65]	433641	1			T1	20		T3	75		T4	9
valid_sources[0x66]	402053	1			T1	5		T3	105		T4	2
valid_sources[0x67]	417260	1			T1	12		T3	65		T4	2
valid_sources[0x68]	391413	1			T1	11		T3	71		T4	5
valid_sources[0x69]	397248	1			T1	28		T3	75		T4	6
valid_sources[0x6a]	376756	1			T1	2		T3	87		T4	1
valid_sources[0x6b]	425300	1			T1	8		T3	77		T4	9
valid_sources[0x6c]	425094	1			T1	5		T3	62		T4	2
valid_sources[0x6d]	397630	1			T1	26		T3	69		T6	125
valid_sources[0x6e]	408785	1			T1	3		T3	54		T4	7
valid_sources[0x6f]	411572	1			T1	8		T3	90		T4	9
valid_sources[0x70]	397020	1			T1	6		T3	72		T4	8
valid_sources[0x71]	428557	1			T1	5		T3	91		T4	7
valid_sources[0x72]	380497	1			T1	26		T3	88		T6	244
valid_sources[0x73]	433344	1			T1	3		T3	99		T4	11
valid_sources[0x74]	397948	1			T1	25		T3	85		T4	2
valid_sources[0x75]	419676	1			T1	6		T3	88		T4	5
valid_sources[0x76]	419931	1			T1	3		T3	78		T6	2271
valid_sources[0x77]	401614	1			T1	24		T3	82		T4	1
valid_sources[0x78]	431791	1			T1	1		T3	58		T4	2
valid_sources[0x79]	394245	1			T1	17		T3	79		T4	7
valid_sources[0x7a]	378909	1			T1	8		T3	67		T4	2
valid_sources[0x7b]	417671	1			T1	9		T3	76		T6	270
valid_sources[0x7c]	378737	1			T1	5		T3	93		T4	6
valid_sources[0x7d]	398145	1			T1	9		T3	83		T6	547
valid_sources[0x7e]	392146	1			T1	1		T3	74		T4	1
valid_sources[0x7f]	487125	1			T1	18		T3	55		T4	6
valid_sources[0x80]	384836	1			T1	12		T3	75		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

21057345

1

T1

51

T2

1

T3

195

values[0x0]

all_enables

biggest_size

4747105

1

T1

70

T2

2

T3

127

values[0x1]

all_enables

biggest_size

4684524

1

T1

36

T2

1

T3

60