Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	15548572	0	0
ctrl_rd_A	2147483647	334918	0	0
intr_enable_rd_A	2147483647	297226	0	0
ovrd_rd_A	2147483647	333271	0	0
timeout_ctrl_rd_A	2147483647	334699	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15548572	0	0
T6	158969	58532	0	0
T7	298622	0	0	0
T8	113390	0	0	0
T9	741313	0	0	0
T10	367906	0	0	0
T11	131790	0	0	0
T12	555432	0	0	0
T14	0	282276	0	0
T17	0	191291	0	0
T21	99816	0	0	0
T29	0	27550	0	0
T30	0	48413	0	0
T31	0	138574	0	0
T32	0	177228	0	0
T33	0	110244	0	0
T34	0	135990	0	0
T35	0	54956	0	0
T36	258565	0	0	0
T37	179729	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	334918	0	0
T30	207172	5322	0	0
T31	481346	0	0	0
T33	0	8561	0	0
T35	0	6631	0	0
T46	0	7156	0	0
T47	0	4105	0	0
T49	0	18648	0	0
T50	0	15246	0	0
T101	0	11990	0	0
T102	0	3301	0	0
T103	0	9730	0	0
T104	174116	0	0	0
T105	154889	0	0	0
T106	105442	0	0	0
T107	345389	0	0	0
T108	166547	0	0	0
T109	53655	0	0	0
T110	811841	0	0	0
T111	165913	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	297226	0	0
T30	207172	4598	0	0
T31	481346	0	0	0
T33	0	7523	0	0
T35	0	5755	0	0
T46	0	6175	0	0
T47	0	3739	0	0
T49	0	16173	0	0
T101	0	10827	0	0
T102	0	2958	0	0
T104	174116	0	0	0
T105	154889	0	0	0
T106	105442	0	0	0
T107	345389	0	0	0
T108	166547	0	0	0
T109	53655	0	0	0
T110	811841	0	0	0
T111	165913	0	0	0
T112	0	8	0	0
T113	0	6	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	333271	0	0
T30	207172	5386	0	0
T31	481346	0	0	0
T33	0	8889	0	0
T35	0	6352	0	0
T46	0	7189	0	0
T47	0	3822	0	0
T49	0	18178	0	0
T50	0	15136	0	0
T101	0	12599	0	0
T102	0	3441	0	0
T103	0	9144	0	0
T104	174116	0	0	0
T105	154889	0	0	0
T106	105442	0	0	0
T107	345389	0	0	0
T108	166547	0	0	0
T109	53655	0	0	0
T110	811841	0	0	0
T111	165913	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	334699	0	0
T30	207172	5132	0	0
T31	481346	0	0	0
T33	0	8739	0	0
T35	0	6453	0	0
T46	0	6850	0	0
T47	0	4307	0	0
T49	0	19200	0	0
T50	0	14696	0	0
T101	0	12112	0	0
T102	0	3050	0	0
T103	0	9475	0	0
T104	174116	0	0	0
T105	154889	0	0	0
T106	105442	0	0	0
T107	345389	0	0	0
T108	166547	0	0	0
T109	53655	0	0	0
T110	811841	0	0	0
T111	165913	0	0	0