Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	64595811	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

28327847

1

T1

493

T2

101

T3

557

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	82267078	1			T1	393532		T2	15376		T3	21409
values[0x0]	5032526	1			T1	170		T2	85		T3	175
values[0x1]	5624054	1			T1	133		T2	73		T3	178

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44798522	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

48125136

1

T1

131494

T2

5246

T3

7612

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	336216	1			T1	1481		T2	59		T3	83
valid_sources[0x01]	328945	1			T1	1481		T2	53		T3	90
valid_sources[0x02]	380125	1			T1	1558		T2	56		T3	70
valid_sources[0x03]	457243	1			T1	1567		T2	52		T3	96
valid_sources[0x04]	339632	1			T1	1476		T2	55		T3	102
valid_sources[0x05]	365450	1			T1	1540		T2	48		T3	77
valid_sources[0x06]	379438	1			T1	1604		T2	54		T3	78
valid_sources[0x07]	368612	1			T1	1541		T2	51		T3	80
valid_sources[0x08]	362527	1			T1	1624		T2	43		T3	96
valid_sources[0x09]	345960	1			T1	1493		T2	59		T3	84
valid_sources[0x0a]	326843	1			T1	1519		T2	57		T3	86
valid_sources[0x0b]	355274	1			T1	1424		T2	73		T3	75
valid_sources[0x0c]	326503	1			T1	1573		T2	67		T3	83
valid_sources[0x0d]	390695	1			T1	1509		T2	45		T3	74
valid_sources[0x0e]	383230	1			T1	1536		T2	43		T3	73
valid_sources[0x0f]	340317	1			T1	1543		T2	45		T3	83
valid_sources[0x10]	387477	1			T1	1527		T2	54		T3	89
valid_sources[0x11]	543604	1			T1	1484		T2	45		T3	84
valid_sources[0x12]	344857	1			T1	1578		T2	46		T3	93
valid_sources[0x13]	326559	1			T1	1630		T2	70		T3	86
valid_sources[0x14]	361763	1			T1	1577		T2	50		T3	83
valid_sources[0x15]	354035	1			T1	1509		T2	93		T3	82
valid_sources[0x16]	330849	1			T1	1566		T2	56		T3	103
valid_sources[0x17]	349385	1			T1	1482		T2	65		T3	80
valid_sources[0x18]	337607	1			T1	1607		T2	73		T3	73
valid_sources[0x19]	480547	1			T1	1488		T2	53		T3	77
valid_sources[0x1a]	352822	1			T1	1554		T2	44		T3	78
valid_sources[0x1b]	355304	1			T1	1529		T2	50		T3	101
valid_sources[0x1c]	361775	1			T1	1582		T2	41		T3	85
valid_sources[0x1d]	324321	1			T1	1629		T2	88		T3	92
valid_sources[0x1e]	348978	1			T1	1542		T2	60		T3	70
valid_sources[0x1f]	359101	1			T1	1471		T2	48		T3	69
valid_sources[0x20]	378772	1			T1	1580		T2	66		T3	70
valid_sources[0x21]	348505	1			T1	1637		T2	48		T3	79
valid_sources[0x22]	324757	1			T1	1504		T2	57		T3	111
valid_sources[0x23]	387321	1			T1	1564		T2	64		T3	88
valid_sources[0x24]	342542	1			T1	1557		T2	97		T3	94
valid_sources[0x25]	388492	1			T1	1528		T2	55		T3	96
valid_sources[0x26]	353287	1			T1	1444		T2	69		T3	81
valid_sources[0x27]	344256	1			T1	1550		T2	64		T3	73
valid_sources[0x28]	409361	1			T1	1497		T2	68		T3	89
valid_sources[0x29]	352352	1			T1	1540		T2	71		T3	92
valid_sources[0x2a]	374629	1			T1	1641		T2	50		T3	83
valid_sources[0x2b]	413870	1			T1	1626		T2	48		T3	87
valid_sources[0x2c]	337598	1			T1	1509		T2	61		T3	92
valid_sources[0x2d]	338762	1			T1	1490		T2	43		T3	92
valid_sources[0x2e]	330973	1			T1	1514		T2	39		T3	88
valid_sources[0x2f]	330711	1			T1	1619		T2	50		T3	73
valid_sources[0x30]	348517	1			T1	1507		T2	55		T3	71
valid_sources[0x31]	398551	1			T1	1473		T2	63		T3	91
valid_sources[0x32]	332980	1			T1	1558		T2	55		T3	85
valid_sources[0x33]	341812	1			T1	1524		T2	50		T3	89
valid_sources[0x34]	401990	1			T1	1515		T2	47		T3	87
valid_sources[0x35]	327549	1			T1	1515		T2	57		T3	79
valid_sources[0x36]	339024	1			T1	1508		T2	28		T3	84
valid_sources[0x37]	346162	1			T1	1564		T2	63		T3	94
valid_sources[0x38]	376478	1			T1	1495		T2	52		T3	77
valid_sources[0x39]	350104	1			T1	1575		T2	46		T3	97
valid_sources[0x3a]	346874	1			T1	1526		T2	83		T3	86
valid_sources[0x3b]	328911	1			T1	1519		T2	56		T3	61
valid_sources[0x3c]	340004	1			T1	1587		T2	73		T3	90
valid_sources[0x3d]	340346	1			T1	1588		T2	89		T3	76
valid_sources[0x3e]	485127	1			T1	1581		T2	76		T3	86
valid_sources[0x3f]	327237	1			T1	1455		T2	59		T3	78
valid_sources[0x40]	358220	1			T1	1558		T2	49		T3	96
valid_sources[0x41]	352097	1			T1	1571		T2	51		T3	84
valid_sources[0x42]	358200	1			T1	1500		T2	85		T3	79
valid_sources[0x43]	335315	1			T1	1531		T2	49		T3	84
valid_sources[0x44]	346188	1			T1	1591		T2	61		T3	89
valid_sources[0x45]	337165	1			T1	1364		T2	74		T3	71
valid_sources[0x46]	351075	1			T1	1551		T2	51		T3	101
valid_sources[0x47]	343939	1			T1	1471		T2	77		T3	82
valid_sources[0x48]	369927	1			T1	1552		T2	48		T3	82
valid_sources[0x49]	359651	1			T1	1549		T2	59		T3	85
valid_sources[0x4a]	339050	1			T1	1510		T2	76		T3	73
valid_sources[0x4b]	393730	1			T1	1396		T2	73		T3	81
valid_sources[0x4c]	335126	1			T1	1627		T2	48		T3	84
valid_sources[0x4d]	337059	1			T1	1577		T2	64		T3	79
valid_sources[0x4e]	358661	1			T1	1591		T2	64		T3	92
valid_sources[0x4f]	368823	1			T1	1551		T2	39		T3	75
valid_sources[0x50]	325778	1			T1	1550		T2	46		T3	95
valid_sources[0x51]	345080	1			T1	1483		T2	60		T3	95
valid_sources[0x52]	362058	1			T1	1507		T2	62		T3	83
valid_sources[0x53]	352194	1			T1	1474		T2	48		T3	98
valid_sources[0x54]	476795	1			T1	1524		T2	69		T3	82
valid_sources[0x55]	338017	1			T1	1531		T2	57		T3	99
valid_sources[0x56]	376987	1			T1	1562		T2	49		T3	80
valid_sources[0x57]	340241	1			T1	1397		T2	59		T3	63
valid_sources[0x58]	345728	1			T1	1514		T2	62		T3	73
valid_sources[0x59]	340409	1			T1	1428		T2	40		T3	99
valid_sources[0x5a]	420977	1			T1	1562		T2	62		T3	109
valid_sources[0x5b]	360345	1			T1	1503		T2	71		T3	84
valid_sources[0x5c]	336551	1			T1	1493		T2	66		T3	81
valid_sources[0x5d]	362785	1			T1	1483		T2	37		T3	82
valid_sources[0x5e]	360602	1			T1	1523		T2	66		T3	80
valid_sources[0x5f]	335426	1			T1	1522		T2	61		T3	92
valid_sources[0x60]	348037	1			T1	1646		T2	54		T3	97
valid_sources[0x61]	344282	1			T1	1403		T2	51		T3	91
valid_sources[0x62]	364565	1			T1	1495		T2	75		T3	84
valid_sources[0x63]	344304	1			T1	1450		T2	72		T3	84
valid_sources[0x64]	359823	1			T1	1570		T2	57		T3	87
valid_sources[0x65]	337323	1			T1	1566		T2	74		T3	87
valid_sources[0x66]	360905	1			T1	1587		T2	61		T3	86
valid_sources[0x67]	339797	1			T1	1539		T2	54		T3	81
valid_sources[0x68]	418347	1			T1	1524		T2	63		T3	93
valid_sources[0x69]	331261	1			T1	1515		T2	80		T3	87
valid_sources[0x6a]	355766	1			T1	1649		T2	42		T3	55
valid_sources[0x6b]	360478	1			T1	1495		T2	50		T3	74
valid_sources[0x6c]	334198	1			T1	1503		T2	72		T3	74
valid_sources[0x6d]	446626	1			T1	1570		T2	44		T3	86
valid_sources[0x6e]	394423	1			T1	1534		T2	44		T3	98
valid_sources[0x6f]	341632	1			T1	1500		T2	54		T3	104
valid_sources[0x70]	435496	1			T1	1602		T2	55		T3	94
valid_sources[0x71]	331352	1			T1	1430		T2	49		T3	89
valid_sources[0x72]	384929	1			T1	1479		T2	77		T3	99
valid_sources[0x73]	331983	1			T1	1489		T2	48		T3	85
valid_sources[0x74]	347232	1			T1	1529		T2	46		T3	91
valid_sources[0x75]	333726	1			T1	1559		T2	79		T3	91
valid_sources[0x76]	366658	1			T1	1478		T2	66		T3	89
valid_sources[0x77]	370559	1			T1	1505		T2	57		T3	67
valid_sources[0x78]	423890	1			T1	1594		T2	83		T3	93
valid_sources[0x79]	430606	1			T1	1521		T2	49		T3	79
valid_sources[0x7a]	370039	1			T1	1572		T2	89		T3	82
valid_sources[0x7b]	365833	1			T1	1452		T2	77		T3	99
valid_sources[0x7c]	330669	1			T1	1596		T2	60		T3	97
valid_sources[0x7d]	407425	1			T1	1657		T2	63		T3	87
valid_sources[0x7e]	340901	1			T1	1555		T2	67		T3	82
valid_sources[0x7f]	349378	1			T1	1516		T2	79		T3	84
valid_sources[0x80]	341340	1			T1	1531		T2	74		T3	90

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18840756

1

T1

380

T2

48

T3

430

values[0x0]

all_enables

biggest_size

4773505

1

T1

78

T2

36

T3

78

values[0x1]

all_enables

biggest_size

4713586

1

T1

35

T2

17

T3

49