Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	15934897	0	0
ctrl_rd_A	2147483647	157995	0	0
intr_enable_rd_A	2147483647	141294	0	0
ovrd_rd_A	2147483647	156458	0	0
timeout_ctrl_rd_A	2147483647	155755	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15934897	0	0
T12	616067	227543	0	0
T13	506333	0	0	0
T14	285720	0	0	0
T17	254685	102137	0	0
T18	0	46361	0	0
T20	0	450575	0	0
T27	0	38435	0	0
T28	0	304528	0	0
T29	0	276102	0	0
T30	0	234356	0	0
T31	0	189957	0	0
T32	0	191798	0	0
T33	780882	0	0	0
T34	219476	0	0	0
T35	64823	0	0	0
T36	123380	0	0	0
T37	284315	0	0	0
T38	309190	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	157995	0	0
T53	798464	7760	0	0
T57	0	3703	0	0
T58	0	6576	0	0
T60	0	5632	0	0
T103	106925	2855	0	0
T104	0	9954	0	0
T105	0	3260	0	0
T106	0	5493	0	0
T107	0	16326	0	0
T108	0	2785	0	0
T109	109865	0	0	0
T110	1031	0	0	0
T111	733051	0	0	0
T112	858399	0	0	0
T113	127275	0	0	0
T114	120448	0	0	0
T115	71376	0	0	0
T116	278180	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	141294	0	0
T53	798464	6897	0	0
T57	0	3416	0	0
T103	106925	2445	0	0
T104	0	8836	0	0
T105	0	2918	0	0
T106	0	5322	0	0
T107	0	14488	0	0
T108	0	2170	0	0
T109	109865	0	0	0
T110	1031	0	0	0
T111	733051	0	0	0
T112	858399	0	0	0
T113	127275	0	0	0
T114	120448	0	0	0
T115	71376	0	0	0
T116	278180	0	0	0
T117	0	5	0	0
T118	0	28	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	156458	0	0
T53	798464	7375	0	0
T57	0	3910	0	0
T58	0	6989	0	0
T60	0	5583	0	0
T103	106925	3273	0	0
T104	0	10241	0	0
T105	0	3109	0	0
T106	0	5641	0	0
T107	0	15760	0	0
T108	0	2574	0	0
T109	109865	0	0	0
T110	1031	0	0	0
T111	733051	0	0	0
T112	858399	0	0	0
T113	127275	0	0	0
T114	120448	0	0	0
T115	71376	0	0	0
T116	278180	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	155755	0	0
T53	798464	7550	0	0
T57	0	3514	0	0
T58	0	6538	0	0
T60	0	5582	0	0
T103	106925	3043	0	0
T104	0	9973	0	0
T105	0	3031	0	0
T106	0	5838	0	0
T107	0	16182	0	0
T108	0	2446	0	0
T109	109865	0	0	0
T110	1031	0	0	0
T111	733051	0	0	0
T112	858399	0	0	0
T113	127275	0	0	0
T114	120448	0	0	0
T115	71376	0	0	0
T116	278180	0	0	0