Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	76579483	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

30057095

1

T1

7

T2

111

T3

86

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	96345387	1			T1	1260		T2	2102		T3	1055
values[0x0]	4866886	1			T1	5		T2	98		T3	106
values[0x1]	5424305	1			T1	3		T2	120		T3	111

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	53118373	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

53518205

1

T1

439

T2

799

T3

444

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	410715	1			T1	9		T3	4		T4	4
valid_sources[0x01]	412933	1			T1	3		T3	9		T4	12
valid_sources[0x02]	412305	1			T1	7		T3	4		T4	8
valid_sources[0x03]	436819	1			T1	1		T3	4		T4	3
valid_sources[0x04]	448596	1			T1	2		T4	8		T5	31
valid_sources[0x05]	416510	1			T1	11		T3	7		T4	6
valid_sources[0x06]	380872	1			T1	1		T3	1		T4	9
valid_sources[0x07]	414127	1			T1	3		T3	2		T4	5
valid_sources[0x08]	399294	1			T1	5		T3	6		T4	12
valid_sources[0x09]	411474	1			T1	6		T3	4		T4	8
valid_sources[0x0a]	481776	1			T1	7		T3	3		T4	12
valid_sources[0x0b]	395373	1			T1	6		T2	1		T3	8
valid_sources[0x0c]	403584	1			T1	2		T3	7		T4	5
valid_sources[0x0d]	421844	1			T1	4		T3	7		T4	12
valid_sources[0x0e]	529716	1			T1	2		T3	6		T4	3
valid_sources[0x0f]	362850	1			T1	6		T3	4		T4	11
valid_sources[0x10]	401207	1			T1	3		T3	5		T4	11
valid_sources[0x11]	403221	1			T1	4		T3	10		T4	8
valid_sources[0x12]	415791	1			T1	4		T3	7		T4	9
valid_sources[0x13]	424337	1			T1	4		T3	1		T4	8
valid_sources[0x14]	423345	1			T1	10		T3	5		T4	4
valid_sources[0x15]	400801	1			T1	2		T3	6		T4	8
valid_sources[0x16]	430840	1			T1	3		T3	9		T4	6
valid_sources[0x17]	390885	1			T1	7		T3	6		T4	8
valid_sources[0x18]	397537	1			T1	3		T3	9		T4	14
valid_sources[0x19]	408804	1			T1	3		T3	2		T4	6
valid_sources[0x1a]	397571	1			T1	1		T3	5		T4	11
valid_sources[0x1b]	399618	1			T1	3		T3	2		T4	10
valid_sources[0x1c]	416636	1			T1	4		T3	5		T4	6
valid_sources[0x1d]	435141	1			T1	1		T3	2		T4	5
valid_sources[0x1e]	403528	1			T1	5		T3	2		T4	5
valid_sources[0x1f]	397386	1			T1	11		T3	1		T4	10
valid_sources[0x20]	467596	1			T1	2		T3	3		T4	6
valid_sources[0x21]	402317	1			T1	6		T3	7		T4	10
valid_sources[0x22]	401299	1			T1	4		T3	3		T4	12
valid_sources[0x23]	457568	1			T1	1		T3	9		T4	9
valid_sources[0x24]	532818	1			T1	4		T3	4		T4	6
valid_sources[0x25]	412244	1			T1	5		T3	1		T4	15
valid_sources[0x26]	381210	1			T3	2		T4	9		T5	39
valid_sources[0x27]	489496	1			T1	1		T3	3		T4	8
valid_sources[0x28]	411358	1			T1	5		T3	6		T4	12
valid_sources[0x29]	380961	1			T1	4		T3	5		T4	13
valid_sources[0x2a]	410797	1			T1	2		T3	10		T4	6
valid_sources[0x2b]	403044	1			T1	1		T3	6		T4	4
valid_sources[0x2c]	392350	1			T1	6		T3	8		T4	10
valid_sources[0x2d]	396083	1			T1	6		T3	6		T4	9
valid_sources[0x2e]	446955	1			T1	7		T3	5		T4	8
valid_sources[0x2f]	398526	1			T1	2		T3	4		T4	4
valid_sources[0x30]	415436	1			T1	2		T3	5		T4	5
valid_sources[0x31]	413707	1			T3	1		T4	6		T5	42
valid_sources[0x32]	433082	1			T1	9		T3	4		T4	4
valid_sources[0x33]	390691	1			T1	8		T3	3		T4	6
valid_sources[0x34]	417898	1			T1	13		T3	4		T4	5
valid_sources[0x35]	436550	1			T1	3		T3	4		T4	9
valid_sources[0x36]	458017	1			T1	2		T3	3		T4	8
valid_sources[0x37]	386396	1			T1	6		T3	3		T4	4
valid_sources[0x38]	403415	1			T1	2		T3	5		T4	14
valid_sources[0x39]	434806	1			T1	2		T3	4		T4	6
valid_sources[0x3a]	402086	1			T3	10		T4	11		T5	38
valid_sources[0x3b]	433731	1			T1	7		T3	4		T4	10
valid_sources[0x3c]	384242	1			T1	16		T3	8		T4	10
valid_sources[0x3d]	427161	1			T1	9		T3	6		T4	12
valid_sources[0x3e]	397530	1			T1	1		T3	1		T4	7
valid_sources[0x3f]	420310	1			T3	11		T4	4		T5	42
valid_sources[0x40]	406688	1			T1	4		T3	7		T4	8
valid_sources[0x41]	458515	1			T1	13		T3	18		T4	7
valid_sources[0x42]	442118	1			T1	2		T3	3		T4	6
valid_sources[0x43]	400167	1			T1	3		T3	2		T4	7
valid_sources[0x44]	441232	1			T1	3		T3	8		T4	4
valid_sources[0x45]	427883	1			T1	6		T3	3		T4	5
valid_sources[0x46]	404661	1			T1	6		T3	3		T4	3
valid_sources[0x47]	394797	1			T1	7		T3	3		T4	9
valid_sources[0x48]	388796	1			T1	1		T3	4		T4	12
valid_sources[0x49]	375928	1			T1	12		T3	8		T4	5
valid_sources[0x4a]	406665	1			T1	1		T3	10		T4	9
valid_sources[0x4b]	407077	1			T1	10		T3	4		T4	9
valid_sources[0x4c]	409419	1			T1	1		T3	5		T4	4
valid_sources[0x4d]	396523	1			T2	2319		T3	3		T4	5
valid_sources[0x4e]	384535	1			T1	6		T3	2		T4	10
valid_sources[0x4f]	425549	1			T3	5		T4	8		T5	46
valid_sources[0x50]	480392	1			T1	11		T4	5		T5	50
valid_sources[0x51]	409568	1			T1	10		T3	11		T4	7
valid_sources[0x52]	472423	1			T1	6		T3	4		T4	9
valid_sources[0x53]	395388	1			T1	6		T3	1		T4	10
valid_sources[0x54]	425967	1			T1	4		T3	2		T4	11
valid_sources[0x55]	422610	1			T1	5		T3	1		T4	8
valid_sources[0x56]	385301	1			T1	2		T3	6		T4	10
valid_sources[0x57]	438401	1			T1	7		T3	11		T4	10
valid_sources[0x58]	418756	1			T1	6		T3	7		T4	8
valid_sources[0x59]	410988	1			T1	1		T3	8		T4	4
valid_sources[0x5a]	449290	1			T1	4		T3	6		T4	11
valid_sources[0x5b]	457773	1			T1	12		T3	6		T4	6
valid_sources[0x5c]	430203	1			T1	9		T3	4		T4	5
valid_sources[0x5d]	414181	1			T1	4		T3	3		T4	11
valid_sources[0x5e]	400998	1			T1	2		T4	6		T5	41
valid_sources[0x5f]	394055	1			T1	1		T3	4		T4	6
valid_sources[0x60]	422248	1			T1	7		T3	2		T4	9
valid_sources[0x61]	479267	1			T1	5		T3	11		T4	7
valid_sources[0x62]	496258	1			T1	6		T3	2		T4	7
valid_sources[0x63]	451149	1			T1	6		T3	3		T4	11
valid_sources[0x64]	411199	1			T1	8		T3	3		T4	11
valid_sources[0x65]	415172	1			T1	9		T3	4		T4	6
valid_sources[0x66]	424351	1			T1	4		T3	3		T4	11
valid_sources[0x67]	433259	1			T1	15		T3	5		T4	7
valid_sources[0x68]	404379	1			T3	3		T4	13		T5	49
valid_sources[0x69]	426714	1			T1	3		T3	4		T4	13
valid_sources[0x6a]	373641	1			T3	8		T4	10		T5	40
valid_sources[0x6b]	432773	1			T1	7		T3	4		T4	5
valid_sources[0x6c]	412089	1			T1	1		T3	8		T4	8
valid_sources[0x6d]	473789	1			T3	3		T4	10		T5	43
valid_sources[0x6e]	425525	1			T1	8		T3	5		T4	7
valid_sources[0x6f]	412690	1			T1	6		T3	3		T4	11
valid_sources[0x70]	461088	1			T1	3		T3	6		T4	7
valid_sources[0x71]	397066	1			T1	2		T3	8		T4	13
valid_sources[0x72]	406533	1			T1	5		T3	7		T4	9
valid_sources[0x73]	481257	1			T1	4		T3	2		T4	8
valid_sources[0x74]	411369	1			T1	4		T3	2		T4	10
valid_sources[0x75]	389327	1			T1	4		T3	4		T4	10
valid_sources[0x76]	417295	1			T1	7		T3	1		T4	9
valid_sources[0x77]	586354	1			T3	4		T4	8		T5	39
valid_sources[0x78]	444198	1			T1	13		T3	7		T4	4
valid_sources[0x79]	471264	1			T1	5		T3	11		T4	10
valid_sources[0x7a]	464131	1			T1	3		T3	3		T4	7
valid_sources[0x7b]	392341	1			T1	1		T3	5		T4	8
valid_sources[0x7c]	414416	1			T1	3		T3	6		T4	4
valid_sources[0x7d]	416422	1			T1	21		T3	4		T4	12
valid_sources[0x7e]	417967	1			T1	25		T3	3		T4	11
valid_sources[0x7f]	426512	1			T1	5		T3	9		T4	11
valid_sources[0x80]	391565	1			T3	1		T4	8		T5	48

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

20919267

1

T1

2

T2

48

T3

16

values[0x0]

all_enables

biggest_size

4600166

1

T1

4

T2

34

T3

45

values[0x1]

all_enables

biggest_size

4537662

1

T1

1

T2

29

T3

25