Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	15047686	0	0
ctrl_rd_A	2147483647	291493	0	0
intr_enable_rd_A	2147483647	257835	0	0
ovrd_rd_A	2147483647	290740	0	0
timeout_ctrl_rd_A	2147483647	287989	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15047686	0	0
T9	812879	242963	0	0
T10	114401	0	0	0
T11	182155	0	0	0
T12	512695	210073	0	0
T13	112915	0	0	0
T14	0	148073	0	0
T20	0	119365	0	0
T22	12888	0	0	0
T23	1228	0	0	0
T29	289071	0	0	0
T30	916090	0	0	0
T31	0	54100	0	0
T32	0	34492	0	0
T33	0	78167	0	0
T34	0	82229	0	0
T35	0	181035	0	0
T36	0	200832	0	0
T37	305280	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	291493	0	0
T20	507714	12739	0	0
T32	0	3862	0	0
T44	406438	0	0	0
T53	0	11064	0	0
T112	0	12824	0	0
T113	0	8457	0	0
T114	0	6924	0	0
T115	0	5976	0	0
T116	0	9328	0	0
T117	0	9046	0	0
T118	0	5041	0	0
T119	282505	0	0	0
T120	673331	0	0	0
T121	190283	0	0	0
T122	489248	0	0	0
T123	145768	0	0	0
T124	22989	0	0	0
T125	135034	0	0	0
T126	333075	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	257835	0	0
T20	507714	11429	0	0
T32	0	3193	0	0
T44	406438	0	0	0
T53	0	9847	0	0
T112	0	12299	0	0
T113	0	7453	0	0
T114	0	5864	0	0
T115	0	5063	0	0
T116	0	8316	0	0
T117	0	7818	0	0
T118	0	4196	0	0
T119	282505	0	0	0
T120	673331	0	0	0
T121	190283	0	0	0
T122	489248	0	0	0
T123	145768	0	0	0
T124	22989	0	0	0
T125	135034	0	0	0
T126	333075	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	290740	0	0
T20	507714	13036	0	0
T32	0	3600	0	0
T44	406438	0	0	0
T53	0	11087	0	0
T112	0	13827	0	0
T113	0	8334	0	0
T114	0	6618	0	0
T115	0	6373	0	0
T116	0	9810	0	0
T117	0	8953	0	0
T118	0	4830	0	0
T119	282505	0	0	0
T120	673331	0	0	0
T121	190283	0	0	0
T122	489248	0	0	0
T123	145768	0	0	0
T124	22989	0	0	0
T125	135034	0	0	0
T126	333075	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	287989	0	0
T20	507714	13031	0	0
T32	0	3669	0	0
T44	406438	0	0	0
T53	0	11447	0	0
T112	0	13223	0	0
T113	0	8637	0	0
T114	0	6473	0	0
T115	0	5898	0	0
T116	0	9127	0	0
T117	0	9527	0	0
T118	0	4914	0	0
T119	282505	0	0	0
T120	673331	0	0	0
T121	190283	0	0	0
T122	489248	0	0	0
T123	145768	0	0	0
T124	22989	0	0	0
T125	135034	0	0	0
T126	333075	0	0	0