Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	64258275	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

14304578

1

T1

3293

T2

74

T3

725323

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	77389987	1			T1	1649		T2	103		T3	164180
values[0x0]	569922	1			T1	1231		T2	29		T3	1656
values[0x1]	602944	1			T1	1405		T2	24		T3	1743

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44436907	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

34125946

1

T1

3672

T2

86

T3

935497

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	277664	1			T1	25		T3	6361		T4	69
valid_sources[0x01]	265775	1			T1	18		T3	6409		T4	12
valid_sources[0x02]	305018	1			T1	7		T3	6450		T4	49
valid_sources[0x03]	268521	1			T1	20		T3	6370		T4	40
valid_sources[0x04]	323719	1			T1	12		T3	6399		T4	66
valid_sources[0x05]	333479	1			T1	21		T3	6401		T4	54
valid_sources[0x06]	358214	1			T1	18		T3	6425		T4	58
valid_sources[0x07]	286744	1			T1	14		T3	6644		T4	52
valid_sources[0x08]	291879	1			T1	24		T3	6637		T4	25
valid_sources[0x09]	284893	1			T1	12		T3	6433		T4	89
valid_sources[0x0a]	333426	1			T1	26		T2	2		T3	6482
valid_sources[0x0b]	313223	1			T1	19		T3	6396		T4	59
valid_sources[0x0c]	294331	1			T1	12		T3	6419		T4	58
valid_sources[0x0d]	280196	1			T1	18		T2	1		T3	6368
valid_sources[0x0e]	339621	1			T1	10		T3	6377		T4	52
valid_sources[0x0f]	368841	1			T1	12		T3	6505		T4	101
valid_sources[0x10]	370020	1			T1	13		T3	6434		T4	40
valid_sources[0x11]	299310	1			T1	14		T3	6359		T4	50
valid_sources[0x12]	295683	1			T1	9		T3	6402		T4	68
valid_sources[0x13]	322929	1			T1	22		T2	1		T3	6294
valid_sources[0x14]	283840	1			T1	15		T3	6252		T4	35
valid_sources[0x15]	354124	1			T1	17		T3	6422		T4	56
valid_sources[0x16]	296961	1			T1	20		T3	6310		T4	55
valid_sources[0x17]	340125	1			T1	23		T2	1		T3	6609
valid_sources[0x18]	269022	1			T1	26		T2	3		T3	6355
valid_sources[0x19]	260231	1			T1	14		T3	6484		T4	81
valid_sources[0x1a]	305048	1			T1	8		T2	2		T3	6432
valid_sources[0x1b]	268846	1			T1	17		T3	6323		T4	49
valid_sources[0x1c]	362981	1			T1	15		T3	6347		T4	42
valid_sources[0x1d]	309643	1			T1	18		T2	1		T3	6283
valid_sources[0x1e]	281007	1			T1	22		T3	6358		T4	71
valid_sources[0x1f]	277331	1			T1	16		T3	6471		T4	51
valid_sources[0x20]	287562	1			T1	17		T3	6290		T4	85
valid_sources[0x21]	342752	1			T1	27		T3	6513		T4	44
valid_sources[0x22]	286742	1			T1	19		T3	6520		T4	21
valid_sources[0x23]	302729	1			T1	14		T3	6420		T4	105
valid_sources[0x24]	368021	1			T1	12		T3	6496		T4	16
valid_sources[0x25]	362775	1			T1	13		T3	6506		T4	78
valid_sources[0x26]	281342	1			T1	16		T3	6351		T4	66
valid_sources[0x27]	279201	1			T1	18		T3	6506		T4	75
valid_sources[0x28]	283313	1			T1	6		T3	6376		T4	13
valid_sources[0x29]	275362	1			T1	19		T3	6463		T4	106
valid_sources[0x2a]	301527	1			T1	14		T3	6450		T4	63
valid_sources[0x2b]	314824	1			T1	9		T3	6341		T4	46
valid_sources[0x2c]	296961	1			T1	21		T2	1		T3	6401
valid_sources[0x2d]	303395	1			T1	15		T3	6330		T4	102
valid_sources[0x2e]	291285	1			T1	19		T2	8		T3	6447
valid_sources[0x2f]	258557	1			T1	16		T3	6456		T4	55
valid_sources[0x30]	295031	1			T1	20		T2	3		T3	6410
valid_sources[0x31]	368861	1			T1	14		T3	6442		T4	77
valid_sources[0x32]	276638	1			T1	14		T3	6370		T4	32
valid_sources[0x33]	312290	1			T1	18		T2	1		T3	6429
valid_sources[0x34]	292729	1			T1	32		T2	1		T3	6520
valid_sources[0x35]	315029	1			T1	18		T3	6306		T4	38
valid_sources[0x36]	304066	1			T1	15		T3	6512		T4	92
valid_sources[0x37]	282703	1			T1	12		T2	1		T3	6575
valid_sources[0x38]	278228	1			T1	12		T3	6560		T4	45
valid_sources[0x39]	303703	1			T1	13		T2	1		T3	6318
valid_sources[0x3a]	330784	1			T1	9		T3	6486		T4	105
valid_sources[0x3b]	331726	1			T1	17		T2	1		T3	6353
valid_sources[0x3c]	363380	1			T1	18		T3	6549		T4	36
valid_sources[0x3d]	336073	1			T1	12		T3	6541		T4	38
valid_sources[0x3e]	271197	1			T1	10		T3	6610		T4	46
valid_sources[0x3f]	283783	1			T1	27		T2	1		T3	6340
valid_sources[0x40]	262645	1			T1	21		T3	6512		T4	33
valid_sources[0x41]	292272	1			T1	11		T3	6318		T4	49
valid_sources[0x42]	292344	1			T1	19		T3	6341		T4	79
valid_sources[0x43]	379015	1			T1	19		T2	3		T3	6433
valid_sources[0x44]	312400	1			T1	12		T3	6405		T4	17
valid_sources[0x45]	265932	1			T1	7		T3	6369		T4	28
valid_sources[0x46]	294215	1			T1	22		T3	6388		T4	61
valid_sources[0x47]	290848	1			T1	23		T2	1		T3	6411
valid_sources[0x48]	272932	1			T1	17		T3	6487		T4	126
valid_sources[0x49]	293865	1			T1	10		T3	6293		T4	21
valid_sources[0x4a]	310499	1			T1	11		T3	6493		T4	53
valid_sources[0x4b]	334232	1			T1	16		T3	6488		T4	52
valid_sources[0x4c]	317387	1			T1	18		T3	6568		T4	26
valid_sources[0x4d]	257872	1			T1	15		T2	3		T3	6353
valid_sources[0x4e]	297986	1			T1	14		T3	6462		T4	26
valid_sources[0x4f]	345408	1			T1	17		T3	6399		T4	49
valid_sources[0x50]	293195	1			T1	12		T2	2		T3	6338
valid_sources[0x51]	326342	1			T1	20		T3	6521		T4	89
valid_sources[0x52]	284681	1			T1	12		T3	6301		T4	34
valid_sources[0x53]	293839	1			T1	16		T2	2		T3	6366
valid_sources[0x54]	332855	1			T1	16		T3	6447		T4	89
valid_sources[0x55]	299193	1			T1	14		T3	6446		T4	29
valid_sources[0x56]	297069	1			T1	10		T2	1		T3	6432
valid_sources[0x57]	295001	1			T1	11		T3	6488		T4	13
valid_sources[0x58]	298471	1			T1	24		T2	1		T3	6374
valid_sources[0x59]	269801	1			T1	16		T3	6418		T4	80
valid_sources[0x5a]	298376	1			T1	17		T3	6456		T4	27
valid_sources[0x5b]	338885	1			T1	16		T2	1		T3	6401
valid_sources[0x5c]	355091	1			T1	19		T2	1		T3	6268
valid_sources[0x5d]	342256	1			T1	8		T3	6381		T4	56
valid_sources[0x5e]	356364	1			T1	21		T3	6458		T4	28
valid_sources[0x5f]	303048	1			T1	20		T3	6425		T4	70
valid_sources[0x60]	282574	1			T1	21		T3	6610		T4	50
valid_sources[0x61]	305955	1			T1	15		T3	6381		T4	9
valid_sources[0x62]	288899	1			T1	22		T3	6319		T4	29
valid_sources[0x63]	323082	1			T1	16		T2	2		T3	6489
valid_sources[0x64]	302599	1			T1	14		T3	6395		T4	31
valid_sources[0x65]	331895	1			T1	7		T3	6263		T4	51
valid_sources[0x66]	303082	1			T1	23		T3	6450		T4	29
valid_sources[0x67]	259470	1			T1	17		T3	6337		T4	48
valid_sources[0x68]	299093	1			T1	14		T2	3		T3	6276
valid_sources[0x69]	308958	1			T1	11		T3	6329		T4	41
valid_sources[0x6a]	303113	1			T1	11		T3	6336		T4	38
valid_sources[0x6b]	299031	1			T1	24		T3	6361		T4	92
valid_sources[0x6c]	310271	1			T1	17		T2	7		T3	6390
valid_sources[0x6d]	268204	1			T1	14		T2	1		T3	6533
valid_sources[0x6e]	329827	1			T1	12		T2	1		T3	6425
valid_sources[0x6f]	278937	1			T1	13		T2	2		T3	6263
valid_sources[0x70]	354331	1			T1	20		T3	6557		T4	48
valid_sources[0x71]	296491	1			T1	15		T2	4		T3	6498
valid_sources[0x72]	367453	1			T1	12		T3	6285		T4	41
valid_sources[0x73]	317474	1			T1	19		T2	2		T3	6432
valid_sources[0x74]	303386	1			T1	20		T2	1		T3	6490
valid_sources[0x75]	308446	1			T1	7		T3	6445		T4	23
valid_sources[0x76]	272202	1			T1	14		T2	3		T3	6598
valid_sources[0x77]	284170	1			T1	15		T2	2		T3	6594
valid_sources[0x78]	283104	1			T1	22		T2	1		T3	6326
valid_sources[0x79]	290422	1			T1	20		T2	2		T3	6355
valid_sources[0x7a]	319013	1			T1	20		T2	3		T3	6320
valid_sources[0x7b]	284188	1			T1	26		T2	1		T3	6470
valid_sources[0x7c]	315697	1			T1	19		T3	6292		T4	45
valid_sources[0x7d]	278351	1			T1	29		T3	6303		T4	30
valid_sources[0x7e]	278355	1			T1	23		T3	6532		T4	27
valid_sources[0x7f]	289722	1			T1	25		T3	6366		T4	84
valid_sources[0x80]	288167	1			T1	8		T3	6472		T4	33

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

13582490

1

T1

869

T2

46

T3

724048

values[0x0]

all_enables

biggest_size

386210

1

T1

1186

T2

18

T3

805

values[0x1]

all_enables

biggest_size

335878

1

T1

1238

T2

10

T3

470