Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	879567	0	0
ctrl_rd_A	2147483647	22556	0	0
intr_enable_rd_A	2147483647	20561	0	0
ovrd_rd_A	2147483647	19791	0	0
timeout_ctrl_rd_A	2147483647	20637	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	879567	0	0
T1	143300	3655	0	0
T2	114456	0	0	0
T3	335217	0	0	0
T4	598135	0	0	0
T5	243223	0	0	0
T6	215711	0	0	0
T7	1293	0	0	0
T8	1209	0	0	0
T9	102429	0	0	0
T10	411978	0	0	0
T20	0	17758	0	0
T22	0	5562	0	0
T28	0	8886	0	0
T29	0	7360	0	0
T30	0	5307	0	0
T31	0	14197	0	0
T32	0	14949	0	0
T33	0	14370	0	0
T34	0	16616	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22556	0	0
T1	143300	559	0	0
T2	114456	0	0	0
T3	335217	0	0	0
T4	598135	0	0	0
T5	243223	0	0	0
T6	215711	0	0	0
T7	1293	0	0	0
T8	1209	0	0	0
T9	102429	0	0	0
T10	411978	0	0	0
T68	0	444	0	0
T91	0	172	0	0
T92	0	122	0	0
T93	0	717	0	0
T94	0	459	0	0
T95	0	460	0	0
T96	0	991	0	0
T97	0	1009	0	0
T98	0	564	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	20561	0	0
T1	143300	375	0	0
T2	114456	0	0	0
T3	335217	0	0	0
T4	598135	0	0	0
T5	243223	0	0	0
T6	215711	0	0	0
T7	1293	0	0	0
T8	1209	0	0	0
T9	102429	0	0	0
T10	411978	0	0	0
T16	0	44	0	0
T68	0	369	0	0
T91	0	131	0	0
T92	0	130	0	0
T93	0	586	0	0
T94	0	438	0	0
T95	0	526	0	0
T96	0	1076	0	0
T97	0	688	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	19791	0	0
T1	143300	393	0	0
T2	114456	0	0	0
T3	335217	0	0	0
T4	598135	0	0	0
T5	243223	0	0	0
T6	215711	0	0	0
T7	1293	0	0	0
T8	1209	0	0	0
T9	102429	0	0	0
T10	411978	0	0	0
T68	0	346	0	0
T91	0	191	0	0
T92	0	213	0	0
T93	0	568	0	0
T94	0	468	0	0
T95	0	609	0	0
T96	0	1058	0	0
T97	0	870	0	0
T98	0	525	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	20637	0	0
T1	143300	429	0	0
T2	114456	0	0	0
T3	335217	0	0	0
T4	598135	0	0	0
T5	243223	0	0	0
T6	215711	0	0	0
T7	1293	0	0	0
T8	1209	0	0	0
T9	102429	0	0	0
T10	411978	0	0	0
T68	0	337	0	0
T91	0	170	0	0
T92	0	167	0	0
T93	0	606	0	0
T94	0	418	0	0
T95	0	556	0	0
T96	0	1017	0	0
T97	0	861	0	0
T98	0	763	0	0