Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	983411	0	0
ctrl_rd_A	2147483647	20930	0	0
intr_enable_rd_A	2147483647	19360	0	0
ovrd_rd_A	2147483647	19267	0	0
timeout_ctrl_rd_A	2147483647	20027	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	983411	0	0
T9	509847	14729	0	0
T10	419486	0	0	0
T11	107986	0	0	0
T12	238579	0	0	0
T13	165777	0	0	0
T15	0	20713	0	0
T17	0	6409	0	0
T20	0	8937	0	0
T27	0	11414	0	0
T28	0	20661	0	0
T29	0	7068	0	0
T30	0	12761	0	0
T31	0	18286	0	0
T32	0	5215	0	0
T33	345262	0	0	0
T34	328169	0	0	0
T35	133255	0	0	0
T36	760485	0	0	0
T37	185898	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	20930	0	0
T9	509847	861	0	0
T10	419486	0	0	0
T11	107986	0	0	0
T12	238579	0	0	0
T13	165777	0	0	0
T27	0	1313	0	0
T32	0	727	0	0
T33	345262	0	0	0
T34	328169	0	0	0
T35	133255	0	0	0
T36	760485	0	0	0
T37	185898	0	0	0
T86	0	343	0	0
T87	0	783	0	0
T88	0	266	0	0
T89	0	468	0	0
T90	0	310	0	0
T91	0	670	0	0
T92	0	622	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	19360	0	0
T9	509847	731	0	0
T10	419486	0	0	0
T11	107986	0	0	0
T12	238579	0	0	0
T13	165777	0	0	0
T27	0	1072	0	0
T32	0	623	0	0
T33	345262	0	0	0
T34	328169	0	0	0
T35	133255	0	0	0
T36	760485	0	0	0
T37	185898	0	0	0
T86	0	383	0	0
T87	0	785	0	0
T88	0	320	0	0
T89	0	375	0	0
T90	0	271	0	0
T91	0	600	0	0
T93	0	7	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	19267	0	0
T9	509847	788	0	0
T10	419486	0	0	0
T11	107986	0	0	0
T12	238579	0	0	0
T13	165777	0	0	0
T27	0	1209	0	0
T32	0	609	0	0
T33	345262	0	0	0
T34	328169	0	0	0
T35	133255	0	0	0
T36	760485	0	0	0
T37	185898	0	0	0
T86	0	439	0	0
T87	0	1025	0	0
T88	0	348	0	0
T89	0	354	0	0
T90	0	335	0	0
T91	0	551	0	0
T92	0	565	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	20027	0	0
T9	509847	891	0	0
T10	419486	0	0	0
T11	107986	0	0	0
T12	238579	0	0	0
T13	165777	0	0	0
T27	0	1295	0	0
T32	0	721	0	0
T33	345262	0	0	0
T34	328169	0	0	0
T35	133255	0	0	0
T36	760485	0	0	0
T37	185898	0	0	0
T86	0	397	0	0
T87	0	872	0	0
T88	0	277	0	0
T89	0	478	0	0
T90	0	352	0	0
T91	0	617	0	0
T92	0	601	0	0