Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	946643	0	0
ctrl_rd_A	2147483647	19228	0	0
intr_enable_rd_A	2147483647	18229	0	0
ovrd_rd_A	2147483647	18080	0	0
timeout_ctrl_rd_A	2147483647	18292	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	946643	0	0
T6	339740	14605	0	0
T7	327892	0	0	0
T8	303990	0	0	0
T9	233437	0	0	0
T10	437142	0	0	0
T11	207967	0	0	0
T12	336187	0	0	0
T13	612140	0	0	0
T14	0	10235	0	0
T15	0	15527	0	0
T17	0	6340	0	0
T19	140959	0	0	0
T22	0	4097	0	0
T30	0	2479	0	0
T31	0	2710	0	0
T32	0	14003	0	0
T33	0	5261	0	0
T34	0	12861	0	0
T35	427137	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	19228	0	0
T14	324535	353	0	0
T15	421999	0	0	0
T21	126209	0	0	0
T22	151144	0	0	0
T23	979	0	0	0
T30	0	238	0	0
T34	0	602	0	0
T38	387370	0	0	0
T82	0	463	0	0
T83	0	1740	0	0
T84	0	243	0	0
T85	0	248	0	0
T86	0	355	0	0
T87	0	600	0	0
T88	0	853	0	0
T89	110853	0	0	0
T90	103174	0	0	0
T91	349746	0	0	0
T92	456962	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	18229	0	0
T14	324535	272	0	0
T15	421999	0	0	0
T21	126209	0	0	0
T22	151144	0	0	0
T23	979	0	0	0
T30	0	277	0	0
T34	0	606	0	0
T38	387370	0	0	0
T82	0	520	0	0
T83	0	1569	0	0
T84	0	295	0	0
T85	0	253	0	0
T86	0	357	0	0
T87	0	487	0	0
T88	0	670	0	0
T89	110853	0	0	0
T90	103174	0	0	0
T91	349746	0	0	0
T92	456962	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	18080	0	0
T14	324535	348	0	0
T15	421999	0	0	0
T21	126209	0	0	0
T22	151144	0	0	0
T23	979	0	0	0
T30	0	237	0	0
T34	0	625	0	0
T38	387370	0	0	0
T82	0	580	0	0
T83	0	1673	0	0
T84	0	316	0	0
T85	0	288	0	0
T86	0	332	0	0
T87	0	582	0	0
T88	0	768	0	0
T89	110853	0	0	0
T90	103174	0	0	0
T91	349746	0	0	0
T92	456962	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	18292	0	0
T14	324535	299	0	0
T15	421999	0	0	0
T21	126209	0	0	0
T22	151144	0	0	0
T23	979	0	0	0
T30	0	310	0	0
T34	0	714	0	0
T38	387370	0	0	0
T82	0	573	0	0
T83	0	1597	0	0
T84	0	282	0	0
T85	0	247	0	0
T86	0	369	0	0
T87	0	614	0	0
T88	0	810	0	0
T89	110853	0	0	0
T90	103174	0	0	0
T91	349746	0	0	0
T92	456962	0	0	0