Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	997373	0	0
ctrl_rd_A	2147483647	21788	0	0
intr_enable_rd_A	2147483647	20441	0	0
ovrd_rd_A	2147483647	21081	0	0
timeout_ctrl_rd_A	2147483647	21377	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	997373	0	0
T14	123791	0	0	0
T15	198802	0	0	0
T16	0	23923	0	0
T18	0	6615	0	0
T25	106651	4333	0	0
T26	0	12263	0	0
T34	0	5668	0	0
T35	0	19139	0	0
T36	0	11779	0	0
T37	0	2819	0	0
T38	0	6136	0	0
T39	0	7453	0	0
T40	321686	0	0	0
T41	285421	0	0	0
T42	17738	0	0	0
T43	415532	0	0	0
T44	313625	0	0	0
T45	62771	0	0	0
T46	416261	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21788	0	0
T18	225280	290	0	0
T21	137163	0	0	0
T23	283086	0	0	0
T37	0	326	0	0
T39	0	846	0	0
T95	0	807	0	0
T96	0	796	0	0
T97	0	970	0	0
T98	0	197	0	0
T99	0	697	0	0
T100	0	686	0	0
T101	0	331	0	0
T102	108530	0	0	0
T103	377328	0	0	0
T104	26594	0	0	0
T105	164029	0	0	0
T106	283183	0	0	0
T107	142630	0	0	0
T108	13392	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	20441	0	0
T18	225280	364	0	0
T21	137163	0	0	0
T23	283086	0	0	0
T37	0	305	0	0
T39	0	666	0	0
T95	0	658	0	0
T96	0	714	0	0
T97	0	848	0	0
T98	0	109	0	0
T99	0	560	0	0
T100	0	648	0	0
T101	0	330	0	0
T102	108530	0	0	0
T103	377328	0	0	0
T104	26594	0	0	0
T105	164029	0	0	0
T106	283183	0	0	0
T107	142630	0	0	0
T108	13392	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21081	0	0
T18	225280	395	0	0
T21	137163	0	0	0
T23	283086	0	0	0
T37	0	438	0	0
T39	0	743	0	0
T95	0	874	0	0
T96	0	975	0	0
T97	0	1002	0	0
T98	0	184	0	0
T99	0	723	0	0
T100	0	736	0	0
T101	0	374	0	0
T102	108530	0	0	0
T103	377328	0	0	0
T104	26594	0	0	0
T105	164029	0	0	0
T106	283183	0	0	0
T107	142630	0	0	0
T108	13392	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21377	0	0
T18	225280	434	0	0
T21	137163	0	0	0
T23	283086	0	0	0
T37	0	368	0	0
T39	0	818	0	0
T95	0	699	0	0
T96	0	970	0	0
T97	0	982	0	0
T98	0	173	0	0
T99	0	746	0	0
T100	0	818	0	0
T101	0	321	0	0
T102	108530	0	0	0
T103	377328	0	0	0
T104	26594	0	0	0
T105	164029	0	0	0
T106	283183	0	0	0
T107	142630	0	0	0
T108	13392	0	0	0