Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	71226105	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16707047

1

T1

137

T2

202

T3

112

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	86748990	1			T1	2292		T2	187		T3	1632
values[0x0]	575632	1			T1	139		T2	204		T3	80
values[0x1]	608530	1			T1	148		T2	183		T3	70

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	49438380	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38494772

1

T1

897

T2

248

T3

636

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	352899	1			T1	2		T3	8		T4	29
valid_sources[0x01]	306918	1			T1	5		T3	10		T6	211
valid_sources[0x02]	343562	1			T1	53		T3	6		T5	1
valid_sources[0x03]	331116	1			T1	9		T2	2		T3	4
valid_sources[0x04]	321271	1			T1	3		T2	35		T3	6
valid_sources[0x05]	333911	1			T1	6		T3	6		T4	3
valid_sources[0x06]	320445	1			T1	19		T3	10		T6	175
valid_sources[0x07]	329428	1			T1	23		T3	3		T4	15
valid_sources[0x08]	319241	1			T1	28		T2	8		T3	6
valid_sources[0x09]	333288	1			T1	9		T3	4		T4	43
valid_sources[0x0a]	328264	1			T1	7		T2	4		T3	9
valid_sources[0x0b]	353685	1			T1	7		T3	2		T4	149
valid_sources[0x0c]	355810	1			T1	25		T3	7		T4	119
valid_sources[0x0d]	313209	1			T2	7		T3	9		T4	127
valid_sources[0x0e]	335515	1			T1	3		T3	9		T4	12
valid_sources[0x0f]	336396	1			T1	2		T3	6		T4	51
valid_sources[0x10]	328479	1			T1	2		T3	10		T4	15
valid_sources[0x11]	332490	1			T1	1		T3	8		T4	152
valid_sources[0x12]	335635	1			T1	5		T2	7		T3	10
valid_sources[0x13]	355374	1			T1	27		T3	10		T4	37
valid_sources[0x14]	350981	1			T1	3		T3	8		T4	1
valid_sources[0x15]	306378	1			T3	8		T4	51		T5	1
valid_sources[0x16]	342399	1			T1	18		T3	8		T4	9
valid_sources[0x17]	369081	1			T1	20		T2	2		T3	3
valid_sources[0x18]	326297	1			T1	1		T3	4		T4	92
valid_sources[0x19]	323457	1			T1	12		T3	8		T4	24
valid_sources[0x1a]	322780	1			T1	23		T2	16		T3	1
valid_sources[0x1b]	368474	1			T1	7		T3	9		T4	20
valid_sources[0x1c]	340428	1			T1	15		T3	6		T4	91
valid_sources[0x1d]	330630	1			T1	2		T3	8		T4	75
valid_sources[0x1e]	426860	1			T1	14		T3	12		T4	20
valid_sources[0x1f]	338155	1			T1	23		T2	6		T3	11
valid_sources[0x20]	343260	1			T1	11		T3	9		T4	76
valid_sources[0x21]	304371	1			T1	16		T3	4		T6	187
valid_sources[0x22]	329970	1			T1	7		T2	7		T3	9
valid_sources[0x23]	318055	1			T1	11		T3	5		T4	134
valid_sources[0x24]	312575	1			T1	19		T3	12		T4	30
valid_sources[0x25]	316977	1			T3	5		T4	40		T6	194
valid_sources[0x26]	323430	1			T1	5		T3	7		T4	92
valid_sources[0x27]	325111	1			T3	14		T4	119		T6	182
valid_sources[0x28]	342294	1			T1	13		T3	5		T4	41
valid_sources[0x29]	322812	1			T1	2		T3	4		T6	213
valid_sources[0x2a]	333856	1			T1	13		T3	5		T4	65
valid_sources[0x2b]	315793	1			T1	9		T3	11		T4	63
valid_sources[0x2c]	307145	1			T1	37		T2	7		T3	2
valid_sources[0x2d]	313602	1			T1	19		T3	6		T4	115
valid_sources[0x2e]	348275	1			T1	17		T3	7		T4	12
valid_sources[0x2f]	322525	1			T1	25		T2	12		T3	5
valid_sources[0x30]	398276	1			T1	4		T3	8		T4	1
valid_sources[0x31]	336894	1			T1	2		T3	12		T4	85
valid_sources[0x32]	359076	1			T1	7		T3	10		T4	1
valid_sources[0x33]	311187	1			T1	7		T3	2		T4	81
valid_sources[0x34]	372955	1			T3	5		T6	160		T8	11
valid_sources[0x35]	346262	1			T1	26		T3	5		T4	13
valid_sources[0x36]	357760	1			T1	6		T3	5		T4	8
valid_sources[0x37]	320676	1			T1	17		T3	10		T4	62
valid_sources[0x38]	317697	1			T2	21		T3	5		T4	51
valid_sources[0x39]	321770	1			T1	11		T3	8		T4	25
valid_sources[0x3a]	382259	1			T1	4		T3	6		T4	192
valid_sources[0x3b]	326700	1			T1	4		T2	5		T3	10
valid_sources[0x3c]	375363	1			T1	3		T3	5		T4	85
valid_sources[0x3d]	355584	1			T1	14		T2	2		T3	4
valid_sources[0x3e]	306939	1			T1	5		T2	7		T3	5
valid_sources[0x3f]	309818	1			T1	18		T3	11		T6	195
valid_sources[0x40]	314471	1			T1	9		T3	7		T4	40
valid_sources[0x41]	336715	1			T1	14		T3	4		T4	2
valid_sources[0x42]	332508	1			T3	9		T4	22		T6	202
valid_sources[0x43]	322205	1			T3	8		T6	211		T8	18
valid_sources[0x44]	309806	1			T1	13		T2	3		T3	5
valid_sources[0x45]	315938	1			T1	11		T3	6		T4	35
valid_sources[0x46]	335720	1			T3	1		T6	181		T8	16
valid_sources[0x47]	337394	1			T1	13		T2	7		T3	12
valid_sources[0x48]	321197	1			T1	4		T3	3		T4	14
valid_sources[0x49]	453864	1			T1	31		T3	6		T4	57
valid_sources[0x4a]	342869	1			T1	20		T2	9		T3	1
valid_sources[0x4b]	360038	1			T1	9		T3	7		T4	123
valid_sources[0x4c]	323529	1			T1	7		T2	3		T3	10
valid_sources[0x4d]	318388	1			T1	15		T3	6		T5	1
valid_sources[0x4e]	337390	1			T3	4		T4	26		T6	131
valid_sources[0x4f]	323906	1			T1	3		T3	7		T4	5
valid_sources[0x50]	354846	1			T1	5		T2	2		T3	13
valid_sources[0x51]	415616	1			T1	9		T2	21		T3	5
valid_sources[0x52]	308122	1			T1	7		T2	5		T3	4
valid_sources[0x53]	323025	1			T1	8		T3	3		T4	116
valid_sources[0x54]	346731	1			T3	13		T4	21		T6	202
valid_sources[0x55]	389727	1			T1	3		T3	10		T4	4
valid_sources[0x56]	348930	1			T1	36		T2	1		T3	15
valid_sources[0x57]	383415	1			T1	8		T3	7		T4	2
valid_sources[0x58]	348048	1			T2	3		T3	5		T4	35
valid_sources[0x59]	371969	1			T1	9		T3	8		T4	4
valid_sources[0x5a]	460546	1			T3	5		T4	3		T6	204
valid_sources[0x5b]	341603	1			T1	9		T2	1		T3	2
valid_sources[0x5c]	343030	1			T1	4		T3	14		T4	89
valid_sources[0x5d]	312707	1			T1	5		T2	11		T3	3
valid_sources[0x5e]	319262	1			T1	6		T4	109		T5	5
valid_sources[0x5f]	357248	1			T1	9		T2	8		T3	3
valid_sources[0x60]	398266	1			T1	3		T2	6		T3	9
valid_sources[0x61]	312633	1			T3	2		T4	114		T6	161
valid_sources[0x62]	349565	1			T1	9		T3	17		T4	71
valid_sources[0x63]	336724	1			T1	8		T3	5		T4	123
valid_sources[0x64]	321290	1			T1	26		T2	10		T3	13
valid_sources[0x65]	387790	1			T3	3		T4	88		T6	181
valid_sources[0x66]	369194	1			T1	11		T2	12		T3	3
valid_sources[0x67]	386167	1			T1	12		T3	4		T4	1
valid_sources[0x68]	351733	1			T1	5		T2	6		T3	5
valid_sources[0x69]	326542	1			T3	9		T4	28		T6	187
valid_sources[0x6a]	309147	1			T1	2		T3	5		T4	125
valid_sources[0x6b]	315492	1			T3	11		T4	22		T6	228
valid_sources[0x6c]	334825	1			T1	6		T3	8		T4	63
valid_sources[0x6d]	351263	1			T1	3		T3	6		T4	44
valid_sources[0x6e]	349988	1			T1	13		T3	4		T4	17
valid_sources[0x6f]	421309	1			T1	16		T2	4		T3	7
valid_sources[0x70]	314718	1			T1	8		T2	19		T3	9
valid_sources[0x71]	320368	1			T3	8		T4	86		T6	214
valid_sources[0x72]	316666	1			T1	11		T3	5		T4	62
valid_sources[0x73]	386700	1			T1	28		T3	2		T4	13
valid_sources[0x74]	368564	1			T1	12		T3	5		T4	33
valid_sources[0x75]	328418	1			T1	1		T3	3		T4	5
valid_sources[0x76]	316575	1			T1	8		T3	8		T4	58
valid_sources[0x77]	314098	1			T1	6		T2	1		T3	2
valid_sources[0x78]	318228	1			T1	9		T3	6		T4	73
valid_sources[0x79]	313798	1			T1	4		T3	5		T4	20
valid_sources[0x7a]	316559	1			T3	9		T6	204		T8	17
valid_sources[0x7b]	321899	1			T1	12		T3	4		T6	186
valid_sources[0x7c]	343872	1			T1	31		T4	101		T6	208
valid_sources[0x7d]	319241	1			T1	5		T2	6		T3	6
valid_sources[0x7e]	321346	1			T1	1		T3	8		T4	76
valid_sources[0x7f]	361718	1			T1	29		T3	7		T4	19
valid_sources[0x80]	327808	1			T1	3		T3	7		T4	43

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15977773

1

T1

56

T2

96

T3

54

values[0x0]

all_enables

biggest_size

389793

1

T1

49

T2

70

T3

40

values[0x1]

all_enables

biggest_size

339481

1

T1

32

T2

36

T3

18