Toggle Coverage for Module :
prim_alert_sender
| Total | Covered | Percent |
Totals |
10 |
10 |
100.00 |
Total Bits |
20 |
20 |
100.00 |
Total Bits 0->1 |
10 |
10 |
100.00 |
Total Bits 1->0 |
10 |
10 |
100.00 |
| | | |
Ports |
10 |
10 |
100.00 |
Port Bits |
20 |
20 |
100.00 |
Port Bits 0->1 |
10 |
10 |
100.00 |
Port Bits 1->0 |
10 |
10 |
100.00 |
Port Details
| | | | | | |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T8,T9,T12 |
Yes |
T1,T2,T3 |
INPUT |
alert_test_i |
Yes |
Yes |
T10,T30,T31 |
Yes |
T10,T30,T31 |
INPUT |
alert_req_i |
Yes |
Yes |
T32,T33,T34 |
Yes |
T32,T33,T34 |
INPUT |
alert_ack_o |
Yes |
Yes |
T32,T33,T34 |
Yes |
T32,T33,T34 |
OUTPUT |
alert_state_o |
Yes |
Yes |
T32,T33,T34 |
Yes |
T32,T33,T34 |
OUTPUT |
alert_rx_i.ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i.ack_p |
Yes |
Yes |
T10,T30,T31 |
Yes |
T10,T30,T31 |
INPUT |
alert_rx_i.ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i.ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_tx_o.alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o.alert_p |
Yes |
Yes |
T10,T30,T31 |
Yes |
T10,T30,T31 |
OUTPUT |