Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	888829	0	0
ctrl_rd_A	2147483647	21558	0	0
intr_enable_rd_A	2147483647	20501	0	0
ovrd_rd_A	2147483647	20017	0	0
timeout_ctrl_rd_A	2147483647	20342	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	888829	0	0
T8	119568	5619	0	0
T9	124942	5164	0	0
T10	1202	0	0	0
T11	183279	0	0	0
T12	239315	6950	0	0
T13	117733	0	0	0
T14	208059	0	0	0
T15	346735	0	0	0
T18	0	9148	0	0
T19	0	16961	0	0
T20	0	5572	0	0
T29	645126	0	0	0
T35	0	4258	0	0
T36	0	11833	0	0
T37	0	10201	0	0
T38	0	3311	0	0
T39	122446	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21558	0	0
T12	239315	842	0	0
T13	117733	0	0	0
T14	208059	0	0	0
T15	346735	0	0	0
T20	0	488	0	0
T29	645126	0	0	0
T36	0	504	0	0
T38	0	398	0	0
T39	122446	0	0	0
T40	134466	0	0	0
T41	85551	0	0	0
T42	208089	0	0	0
T43	178854	0	0	0
T85	0	374	0	0
T86	0	650	0	0
T87	0	311	0	0
T88	0	108	0	0
T89	0	1244	0	0
T90	0	805	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	20501	0	0
T12	239315	791	0	0
T13	117733	0	0	0
T14	208059	0	0	0
T15	346735	0	0	0
T20	0	479	0	0
T29	645126	0	0	0
T36	0	453	0	0
T38	0	425	0	0
T39	122446	0	0	0
T40	134466	0	0	0
T41	85551	0	0	0
T42	208089	0	0	0
T43	178854	0	0	0
T85	0	304	0	0
T86	0	585	0	0
T87	0	305	0	0
T88	0	108	0	0
T89	0	1014	0	0
T91	0	12	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	20017	0	0
T12	239315	823	0	0
T13	117733	0	0	0
T14	208059	0	0	0
T15	346735	0	0	0
T20	0	461	0	0
T29	645126	0	0	0
T36	0	435	0	0
T38	0	413	0	0
T39	122446	0	0	0
T40	134466	0	0	0
T41	85551	0	0	0
T42	208089	0	0	0
T43	178854	0	0	0
T85	0	359	0	0
T86	0	555	0	0
T87	0	257	0	0
T88	0	110	0	0
T89	0	1087	0	0
T90	0	844	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	20342	0	0
T12	239315	856	0	0
T13	117733	0	0	0
T14	208059	0	0	0
T15	346735	0	0	0
T20	0	546	0	0
T29	645126	0	0	0
T36	0	553	0	0
T38	0	365	0	0
T39	122446	0	0	0
T40	134466	0	0	0
T41	85551	0	0	0
T42	208089	0	0	0
T43	178854	0	0	0
T85	0	398	0	0
T86	0	582	0	0
T87	0	288	0	0
T88	0	64	0	0
T89	0	1021	0	0
T90	0	848	0	0