Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	61607996	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

13378132

1

T1

60

T2

32

T3

6936

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	73790807	1			T1	96715		T2	2134		T3	4223
values[0x0]	580558	1			T1	39		T2	26		T3	2678
values[0x1]	614763	1			T1	43		T2	17		T3	2921

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42544767	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

32441361

1

T1

48383

T2

741

T3

7966

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	266014	1			T2	6		T3	57		T4	1
valid_sources[0x01]	278701	1			T2	12		T3	42		T7	31
valid_sources[0x02]	276927	1			T3	47		T7	22		T8	3
valid_sources[0x03]	277688	1			T2	6		T3	50		T7	38
valid_sources[0x04]	284434	1			T2	3		T3	33		T4	2
valid_sources[0x05]	293494	1			T2	36		T3	45		T7	60
valid_sources[0x06]	335385	1			T2	1		T3	32		T7	39
valid_sources[0x07]	297654	1			T2	45		T3	22		T7	32
valid_sources[0x08]	288790	1			T3	49		T7	47		T8	5
valid_sources[0x09]	399634	1			T1	5049		T3	39		T6	15565
valid_sources[0x0a]	272961	1			T3	16		T7	37		T8	2
valid_sources[0x0b]	279210	1			T2	39		T3	41		T7	21
valid_sources[0x0c]	277471	1			T2	1		T3	40		T4	2
valid_sources[0x0d]	263810	1			T2	5		T3	29		T7	39
valid_sources[0x0e]	318798	1			T3	35		T7	42		T8	2
valid_sources[0x0f]	263683	1			T2	15		T3	33		T6	1
valid_sources[0x10]	281577	1			T2	2		T3	50		T4	1
valid_sources[0x11]	254805	1			T2	1		T3	40		T7	37
valid_sources[0x12]	283777	1			T3	41		T7	34		T8	5
valid_sources[0x13]	315564	1			T3	36		T7	36		T8	1
valid_sources[0x14]	317781	1			T3	40		T7	41		T8	4
valid_sources[0x15]	277703	1			T2	13		T3	36		T4	1
valid_sources[0x16]	294645	1			T2	5		T3	36		T7	39
valid_sources[0x17]	284299	1			T2	18		T3	30		T7	55
valid_sources[0x18]	294185	1			T2	31		T3	36		T7	39
valid_sources[0x19]	280265	1			T2	45		T3	37		T5	45
valid_sources[0x1a]	320755	1			T1	5049		T2	27		T3	30
valid_sources[0x1b]	284018	1			T3	46		T7	10		T10	16
valid_sources[0x1c]	270268	1			T3	32		T7	56		T8	6
valid_sources[0x1d]	274299	1			T3	34		T7	68		T8	6
valid_sources[0x1e]	271468	1			T2	4		T3	55		T4	2
valid_sources[0x1f]	275057	1			T3	42		T7	24		T12	12
valid_sources[0x20]	315138	1			T2	3		T3	37		T4	2
valid_sources[0x21]	286048	1			T2	11		T3	45		T4	3
valid_sources[0x22]	293615	1			T3	46		T7	33		T8	1
valid_sources[0x23]	285420	1			T3	37		T6	1		T7	37
valid_sources[0x24]	298531	1			T3	36		T7	24		T8	7
valid_sources[0x25]	325713	1			T2	38		T3	34		T7	37
valid_sources[0x26]	260165	1			T3	44		T7	17		T8	2
valid_sources[0x27]	325433	1			T2	34		T3	33		T7	50
valid_sources[0x28]	342529	1			T2	11		T3	36		T7	27
valid_sources[0x29]	356901	1			T2	33		T3	31		T7	65
valid_sources[0x2a]	284049	1			T2	6		T3	48		T7	25
valid_sources[0x2b]	279701	1			T1	5291		T2	11		T3	41
valid_sources[0x2c]	260705	1			T2	4		T3	46		T7	57
valid_sources[0x2d]	337334	1			T2	8		T3	31		T4	1
valid_sources[0x2e]	312983	1			T1	1		T3	49		T7	48
valid_sources[0x2f]	315055	1			T2	24		T3	34		T7	11
valid_sources[0x30]	280718	1			T2	16		T3	38		T4	3
valid_sources[0x31]	264297	1			T2	39		T3	39		T6	1
valid_sources[0x32]	298434	1			T2	20		T3	46		T7	35
valid_sources[0x33]	302466	1			T2	12		T3	34		T7	25
valid_sources[0x34]	274073	1			T2	3		T3	22		T4	1
valid_sources[0x35]	356939	1			T2	5		T3	39		T7	52
valid_sources[0x36]	365435	1			T2	37		T3	38		T7	17
valid_sources[0x37]	261137	1			T2	7		T3	43		T7	70
valid_sources[0x38]	276698	1			T2	9		T3	46		T7	33
valid_sources[0x39]	286188	1			T2	6		T3	36		T7	25
valid_sources[0x3a]	314009	1			T2	2		T3	45		T7	23
valid_sources[0x3b]	289646	1			T3	52		T4	2		T7	71
valid_sources[0x3c]	268632	1			T2	14		T3	35		T7	29
valid_sources[0x3d]	315531	1			T3	36		T7	41		T8	9
valid_sources[0x3e]	345345	1			T2	14		T3	42		T4	1
valid_sources[0x3f]	271776	1			T3	41		T7	42		T8	4
valid_sources[0x40]	278326	1			T3	37		T4	1		T7	63
valid_sources[0x41]	290018	1			T2	41		T3	35		T7	35
valid_sources[0x42]	299820	1			T2	26		T3	36		T7	18
valid_sources[0x43]	267822	1			T3	24		T4	1		T7	51
valid_sources[0x44]	269889	1			T3	44		T7	27		T8	1
valid_sources[0x45]	276874	1			T2	1		T3	24		T7	44
valid_sources[0x46]	305849	1			T2	9		T3	45		T4	1
valid_sources[0x47]	280330	1			T2	5		T3	40		T7	57
valid_sources[0x48]	318803	1			T3	42		T7	62		T8	4
valid_sources[0x49]	295532	1			T3	57		T7	27		T8	4
valid_sources[0x4a]	253423	1			T2	12		T3	37		T7	63
valid_sources[0x4b]	276635	1			T2	8		T3	35		T7	43
valid_sources[0x4c]	341447	1			T2	3		T3	34		T4	1
valid_sources[0x4d]	326197	1			T2	14		T3	42		T7	44
valid_sources[0x4e]	337255	1			T3	36		T7	32		T8	9
valid_sources[0x4f]	279326	1			T2	10		T3	29		T7	56
valid_sources[0x50]	277080	1			T3	35		T7	49		T8	2
valid_sources[0x51]	265739	1			T3	27		T6	1		T7	12
valid_sources[0x52]	265128	1			T3	42		T7	24		T8	4
valid_sources[0x53]	280407	1			T2	13		T3	42		T7	47
valid_sources[0x54]	280081	1			T3	38		T7	36		T8	1
valid_sources[0x55]	363834	1			T1	323		T2	2		T3	26
valid_sources[0x56]	386299	1			T2	3		T3	42		T4	2
valid_sources[0x57]	285657	1			T3	60		T4	2		T7	31
valid_sources[0x58]	286858	1			T3	26		T7	24		T8	1
valid_sources[0x59]	251980	1			T2	21		T3	41		T4	1
valid_sources[0x5a]	339172	1			T3	29		T7	60		T8	3
valid_sources[0x5b]	275520	1			T2	26		T3	44		T4	1
valid_sources[0x5c]	282732	1			T2	10		T3	53		T4	1
valid_sources[0x5d]	297411	1			T3	40		T7	54		T8	1
valid_sources[0x5e]	271662	1			T2	20		T3	28		T7	15
valid_sources[0x5f]	322663	1			T2	10		T3	42		T4	1
valid_sources[0x60]	250079	1			T2	3		T3	36		T7	37
valid_sources[0x61]	303484	1			T2	5		T3	48		T7	58
valid_sources[0x62]	248326	1			T2	14		T3	37		T4	1
valid_sources[0x63]	416701	1			T2	7		T3	46		T7	23
valid_sources[0x64]	295966	1			T2	2		T3	48		T7	35
valid_sources[0x65]	286317	1			T2	7		T3	40		T7	45
valid_sources[0x66]	274159	1			T3	42		T7	44		T8	4
valid_sources[0x67]	275932	1			T2	8		T3	39		T7	29
valid_sources[0x68]	282336	1			T2	5		T3	30		T7	32
valid_sources[0x69]	303975	1			T2	3		T3	45		T7	26
valid_sources[0x6a]	302645	1			T2	24		T3	34		T4	3
valid_sources[0x6b]	293644	1			T2	27		T3	28		T4	2
valid_sources[0x6c]	267579	1			T3	33		T7	34		T8	1
valid_sources[0x6d]	254890	1			T2	3		T3	47		T7	29
valid_sources[0x6e]	277746	1			T2	1		T3	38		T4	2
valid_sources[0x6f]	273858	1			T2	13		T3	30		T7	39
valid_sources[0x70]	293808	1			T3	39		T7	40		T10	2
valid_sources[0x71]	274446	1			T2	35		T3	40		T4	2
valid_sources[0x72]	281614	1			T1	5049		T2	4		T3	45
valid_sources[0x73]	276735	1			T3	41		T4	1		T7	21
valid_sources[0x74]	266657	1			T1	1		T3	53		T7	30
valid_sources[0x75]	318937	1			T2	20		T3	33		T7	43
valid_sources[0x76]	289721	1			T2	4		T3	32		T4	1
valid_sources[0x77]	291293	1			T1	5290		T2	48		T3	45
valid_sources[0x78]	300945	1			T3	45		T7	37		T8	1
valid_sources[0x79]	259942	1			T3	45		T7	43		T8	2
valid_sources[0x7a]	255975	1			T2	6		T3	44		T7	21
valid_sources[0x7b]	272555	1			T2	1		T3	63		T7	21
valid_sources[0x7c]	260422	1			T3	44		T7	33		T8	8
valid_sources[0x7d]	289588	1			T1	5292		T2	41		T3	29
valid_sources[0x7e]	306096	1			T2	12		T3	36		T7	45
valid_sources[0x7f]	281123	1			T2	16		T3	44		T7	43
valid_sources[0x80]	304149	1			T2	3		T3	52		T7	54

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

12620447

1

T2

2

T3

1707

T4

18

values[0x0]

all_enables

biggest_size

403288

1

T1

29

T2

17

T3

2637

values[0x1]

all_enables

biggest_size

354397

1

T1

31

T2

13

T3

2592