Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	949029	0	0
ctrl_rd_A	2147483647	18119	0	0
intr_enable_rd_A	2147483647	16960	0	0
ovrd_rd_A	2147483647	16990	0	0
timeout_ctrl_rd_A	2147483647	16896	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	949029	0	0
T3	188180	9256	0	0
T4	225365	0	0	0
T5	157655	0	0	0
T6	197436	0	0	0
T7	130927	4655	0	0
T8	16141	0	0	0
T9	158249	0	0	0
T10	777993	0	0	0
T11	452716	0	0	0
T16	0	10221	0	0
T19	617897	0	0	0
T21	0	6363	0	0
T30	0	6578	0	0
T31	0	8780	0	0
T32	0	17654	0	0
T33	0	7231	0	0
T34	0	7228	0	0
T35	0	7632	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	18119	0	0
T33	278672	738	0	0
T34	215385	239	0	0
T35	0	747	0	0
T100	0	177	0	0
T101	0	770	0	0
T102	0	1125	0	0
T103	0	788	0	0
T104	0	422	0	0
T105	0	453	0	0
T106	0	1148	0	0
T107	84278	0	0	0
T108	235085	0	0	0
T109	472649	0	0	0
T110	114455	0	0	0
T111	838253	0	0	0
T112	11057	0	0	0
T113	413926	0	0	0
T114	145301	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16960	0	0
T33	278672	800	0	0
T34	215385	249	0	0
T35	0	773	0	0
T100	0	152	0	0
T101	0	659	0	0
T102	0	915	0	0
T103	0	619	0	0
T104	0	391	0	0
T105	0	381	0	0
T107	84278	0	0	0
T108	235085	0	0	0
T109	472649	0	0	0
T110	114455	0	0	0
T111	838253	0	0	0
T112	11057	0	0	0
T113	413926	0	0	0
T114	145301	0	0	0
T115	0	3	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16990	0	0
T33	278672	884	0	0
T34	215385	256	0	0
T35	0	874	0	0
T100	0	140	0	0
T101	0	701	0	0
T102	0	1240	0	0
T103	0	807	0	0
T104	0	444	0	0
T105	0	550	0	0
T106	0	1210	0	0
T107	84278	0	0	0
T108	235085	0	0	0
T109	472649	0	0	0
T110	114455	0	0	0
T111	838253	0	0	0
T112	11057	0	0	0
T113	413926	0	0	0
T114	145301	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16896	0	0
T33	278672	898	0	0
T34	215385	279	0	0
T35	0	720	0	0
T100	0	163	0	0
T101	0	594	0	0
T102	0	1020	0	0
T103	0	790	0	0
T104	0	480	0	0
T105	0	415	0	0
T106	0	1168	0	0
T107	84278	0	0	0
T108	235085	0	0	0
T109	472649	0	0	0
T110	114455	0	0	0
T111	838253	0	0	0
T112	11057	0	0	0
T113	413926	0	0	0
T114	145301	0	0	0