Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66334758	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

14494134

1

T1

7647

T2

177

T3

4921

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	79567469	1			T1	18871		T2	3063		T3	10216
values[0x0]	611271	1			T1	2750		T2	97		T3	2018
values[0x1]	650152	1			T1	3102		T2	94		T3	2221

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45867571	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

34961321

1

T1

13345

T2

1137

T3

8086

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	286715	1			T1	128		T3	57		T4	22
valid_sources[0x01]	281705	1			T1	108		T2	8		T3	51
valid_sources[0x02]	281134	1			T1	109		T3	56		T4	25
valid_sources[0x03]	314421	1			T1	129		T3	56		T4	18
valid_sources[0x04]	295130	1			T1	98		T2	64		T3	59
valid_sources[0x05]	287994	1			T1	88		T3	53		T4	27
valid_sources[0x06]	297874	1			T1	104		T2	23		T3	63
valid_sources[0x07]	339916	1			T1	97		T2	18		T3	72
valid_sources[0x08]	318210	1			T1	124		T2	8		T3	66
valid_sources[0x09]	323736	1			T1	82		T3	59		T4	13
valid_sources[0x0a]	339291	1			T1	71		T2	14		T3	52
valid_sources[0x0b]	319951	1			T1	120		T2	5		T3	48
valid_sources[0x0c]	311753	1			T1	87		T2	9		T3	55
valid_sources[0x0d]	302419	1			T1	84		T2	2		T3	51
valid_sources[0x0e]	301151	1			T1	105		T2	35		T3	50
valid_sources[0x0f]	289453	1			T1	101		T3	44		T4	11
valid_sources[0x10]	294456	1			T1	119		T3	55		T4	28
valid_sources[0x11]	290127	1			T1	102		T2	3		T3	42
valid_sources[0x12]	417478	1			T1	103		T2	2		T3	68
valid_sources[0x13]	277976	1			T1	67		T2	27		T3	56
valid_sources[0x14]	292856	1			T1	105		T2	5		T3	40
valid_sources[0x15]	293983	1			T1	107		T2	25		T3	63
valid_sources[0x16]	288635	1			T1	106		T2	2		T3	59
valid_sources[0x17]	349133	1			T1	131		T3	51		T4	11
valid_sources[0x18]	347120	1			T1	94		T2	2		T3	71
valid_sources[0x19]	297108	1			T1	103		T2	46		T3	75
valid_sources[0x1a]	284465	1			T1	113		T2	13		T3	51
valid_sources[0x1b]	291246	1			T1	109		T2	9		T3	56
valid_sources[0x1c]	300710	1			T1	96		T2	10		T3	56
valid_sources[0x1d]	308892	1			T1	95		T2	9		T3	76
valid_sources[0x1e]	295302	1			T1	119		T2	46		T3	47
valid_sources[0x1f]	327935	1			T1	127		T2	38		T3	46
valid_sources[0x20]	283456	1			T1	93		T3	64		T4	8
valid_sources[0x21]	310750	1			T1	94		T2	38		T3	58
valid_sources[0x22]	311421	1			T1	77		T3	48		T4	6
valid_sources[0x23]	329281	1			T1	91		T2	8		T3	74
valid_sources[0x24]	285948	1			T1	105		T2	27		T3	57
valid_sources[0x25]	431753	1			T1	94		T2	16		T3	37
valid_sources[0x26]	291937	1			T1	96		T2	8		T3	49
valid_sources[0x27]	276403	1			T1	99		T3	71		T4	15
valid_sources[0x28]	297040	1			T1	103		T2	2		T3	48
valid_sources[0x29]	276552	1			T1	107		T2	7		T3	56
valid_sources[0x2a]	290017	1			T1	102		T3	78		T4	10
valid_sources[0x2b]	382439	1			T1	95		T3	54		T4	19
valid_sources[0x2c]	285983	1			T1	122		T3	48		T4	12
valid_sources[0x2d]	298295	1			T1	89		T2	20		T3	59
valid_sources[0x2e]	290473	1			T1	117		T2	11		T3	46
valid_sources[0x2f]	295658	1			T1	107		T2	27		T3	56
valid_sources[0x30]	293769	1			T1	92		T2	9		T3	45
valid_sources[0x31]	299807	1			T1	75		T3	76		T4	16
valid_sources[0x32]	363515	1			T1	65		T2	78		T3	66
valid_sources[0x33]	279849	1			T1	106		T2	2		T3	56
valid_sources[0x34]	336428	1			T1	109		T2	19		T3	67
valid_sources[0x35]	352930	1			T1	107		T2	38		T3	69
valid_sources[0x36]	292905	1			T1	73		T2	5		T3	74
valid_sources[0x37]	297923	1			T1	116		T2	65		T3	54
valid_sources[0x38]	304987	1			T1	106		T2	2		T3	67
valid_sources[0x39]	482841	1			T1	84		T2	18		T3	60
valid_sources[0x3a]	278506	1			T1	69		T3	53		T4	10
valid_sources[0x3b]	313990	1			T1	94		T3	83		T4	9
valid_sources[0x3c]	300055	1			T1	105		T3	55		T4	21
valid_sources[0x3d]	335206	1			T1	96		T2	22		T3	52
valid_sources[0x3e]	308267	1			T1	86		T2	26		T3	64
valid_sources[0x3f]	281728	1			T1	100		T2	40		T3	51
valid_sources[0x40]	338826	1			T1	121		T2	4		T3	47
valid_sources[0x41]	288457	1			T1	104		T2	11		T3	66
valid_sources[0x42]	345650	1			T1	107		T3	58		T4	15
valid_sources[0x43]	305590	1			T1	103		T2	5		T3	64
valid_sources[0x44]	298111	1			T1	135		T2	8		T3	68
valid_sources[0x45]	315842	1			T1	79		T2	6		T3	53
valid_sources[0x46]	339765	1			T1	94		T2	21		T3	52
valid_sources[0x47]	343677	1			T1	88		T3	49		T4	13
valid_sources[0x48]	296196	1			T1	102		T3	55		T4	4
valid_sources[0x49]	319313	1			T1	113		T2	21		T3	64
valid_sources[0x4a]	291573	1			T1	95		T3	46		T4	9
valid_sources[0x4b]	376349	1			T1	95		T2	20		T3	49
valid_sources[0x4c]	282736	1			T1	78		T2	13		T3	59
valid_sources[0x4d]	309366	1			T1	114		T2	41		T3	42
valid_sources[0x4e]	306427	1			T1	74		T3	64		T4	19
valid_sources[0x4f]	406879	1			T1	69		T2	2		T3	47
valid_sources[0x50]	287967	1			T1	85		T2	27		T3	68
valid_sources[0x51]	332056	1			T1	94		T2	12		T3	57
valid_sources[0x52]	317020	1			T1	81		T3	63		T4	11
valid_sources[0x53]	291418	1			T1	116		T2	9		T3	37
valid_sources[0x54]	309062	1			T1	88		T2	24		T3	56
valid_sources[0x55]	303516	1			T1	84		T2	26		T3	53
valid_sources[0x56]	283510	1			T1	97		T2	20		T3	83
valid_sources[0x57]	288731	1			T1	88		T2	5		T3	61
valid_sources[0x58]	313282	1			T1	71		T2	13		T3	62
valid_sources[0x59]	317550	1			T1	94		T3	50		T4	13
valid_sources[0x5a]	431044	1			T1	96		T2	13		T3	53
valid_sources[0x5b]	297652	1			T1	108		T2	5		T3	47
valid_sources[0x5c]	291337	1			T1	93		T2	9		T3	67
valid_sources[0x5d]	296282	1			T1	122		T3	57		T4	20
valid_sources[0x5e]	289350	1			T1	109		T2	32		T3	49
valid_sources[0x5f]	360462	1			T1	80		T2	9		T3	80
valid_sources[0x60]	314323	1			T1	83		T2	6		T3	66
valid_sources[0x61]	336819	1			T1	113		T2	33		T3	54
valid_sources[0x62]	303067	1			T1	113		T2	38		T3	55
valid_sources[0x63]	326544	1			T1	83		T2	20		T3	53
valid_sources[0x64]	334319	1			T1	106		T2	21		T3	64
valid_sources[0x65]	433320	1			T1	130		T3	56		T4	16
valid_sources[0x66]	292306	1			T1	96		T2	27		T3	69
valid_sources[0x67]	306589	1			T1	84		T2	14		T3	67
valid_sources[0x68]	291673	1			T1	76		T3	55		T4	8
valid_sources[0x69]	303423	1			T1	98		T3	61		T4	16
valid_sources[0x6a]	309568	1			T1	90		T2	5		T3	55
valid_sources[0x6b]	324252	1			T1	76		T2	27		T3	64
valid_sources[0x6c]	280789	1			T1	86		T3	61		T4	7
valid_sources[0x6d]	304585	1			T1	82		T3	52		T4	10
valid_sources[0x6e]	300552	1			T1	92		T2	4		T3	60
valid_sources[0x6f]	286635	1			T1	96		T2	23		T3	54
valid_sources[0x70]	298224	1			T1	74		T2	10		T3	64
valid_sources[0x71]	281116	1			T1	125		T2	12		T3	59
valid_sources[0x72]	290950	1			T1	75		T2	15		T3	52
valid_sources[0x73]	277911	1			T1	119		T3	51		T4	12
valid_sources[0x74]	385227	1			T1	95		T2	22		T3	42
valid_sources[0x75]	352391	1			T1	119		T3	55		T4	10
valid_sources[0x76]	355220	1			T1	89		T2	9		T3	39
valid_sources[0x77]	296250	1			T1	81		T2	21		T3	35
valid_sources[0x78]	298296	1			T1	104		T2	8		T3	50
valid_sources[0x79]	290869	1			T1	92		T2	11		T3	38
valid_sources[0x7a]	303720	1			T1	88		T2	6		T3	73
valid_sources[0x7b]	314128	1			T1	101		T3	61		T4	12
valid_sources[0x7c]	280172	1			T1	95		T2	39		T3	53
valid_sources[0x7d]	292017	1			T1	102		T2	5		T3	59
valid_sources[0x7e]	294178	1			T1	117		T3	56		T4	9
valid_sources[0x7f]	309358	1			T1	101		T2	20		T3	48
valid_sources[0x80]	287745	1			T1	81		T2	8		T3	53

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

13677980

1

T1

2471

T2

123

T3

1219

values[0x0]

all_enables

biggest_size

432323

1

T1

2601

T2

37

T3

1852

values[0x1]

all_enables

biggest_size

383831

1

T1

2575

T2

17

T3

1850