Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1032900	0	0
ctrl_rd_A	2147483647	18047	0	0
intr_enable_rd_A	2147483647	16672	0	0
ovrd_rd_A	2147483647	15972	0	0
timeout_ctrl_rd_A	2147483647	16436	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1032900	0	0
T1	220423	9746	0	0
T2	443148	0	0	0
T3	190434	5655	0	0
T4	801566	0	0	0
T5	638521	0	0	0
T6	370841	0	0	0
T7	133890	0	0	0
T8	615814	0	0	0
T9	590181	0	0	0
T10	670933	0	0	0
T15	0	18501	0	0
T18	0	7434	0	0
T21	0	6393	0	0
T30	0	6776	0	0
T31	0	10476	0	0
T32	0	19974	0	0
T33	0	11358	0	0
T34	0	6694	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	18047	0	0
T3	190434	255	0	0
T4	801566	0	0	0
T5	638521	0	0	0
T6	370841	0	0	0
T7	133890	0	0	0
T8	615814	0	0	0
T9	590181	0	0	0
T10	670933	0	0	0
T21	167502	0	0	0
T30	0	296	0	0
T34	0	395	0	0
T35	267131	0	0	0
T82	0	1003	0	0
T83	0	473	0	0
T84	0	504	0	0
T85	0	472	0	0
T86	0	536	0	0
T87	0	859	0	0
T88	0	1174	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16672	0	0
T3	190434	315	0	0
T4	801566	0	0	0
T5	638521	0	0	0
T6	370841	0	0	0
T7	133890	0	0	0
T8	615814	0	0	0
T9	590181	0	0	0
T10	670933	0	0	0
T21	167502	0	0	0
T23	0	30	0	0
T30	0	307	0	0
T34	0	437	0	0
T35	267131	0	0	0
T82	0	970	0	0
T83	0	436	0	0
T84	0	446	0	0
T85	0	404	0	0
T86	0	395	0	0
T89	0	7	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15972	0	0
T3	190434	304	0	0
T4	801566	0	0	0
T5	638521	0	0	0
T6	370841	0	0	0
T7	133890	0	0	0
T8	615814	0	0	0
T9	590181	0	0	0
T10	670933	0	0	0
T21	167502	0	0	0
T30	0	309	0	0
T34	0	524	0	0
T35	267131	0	0	0
T82	0	1088	0	0
T83	0	499	0	0
T84	0	504	0	0
T85	0	409	0	0
T86	0	501	0	0
T87	0	879	0	0
T88	0	963	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16436	0	0
T3	190434	268	0	0
T4	801566	0	0	0
T5	638521	0	0	0
T6	370841	0	0	0
T7	133890	0	0	0
T8	615814	0	0	0
T9	590181	0	0	0
T10	670933	0	0	0
T21	167502	0	0	0
T30	0	269	0	0
T34	0	478	0	0
T35	267131	0	0	0
T82	0	1253	0	0
T83	0	492	0	0
T84	0	532	0	0
T85	0	441	0	0
T86	0	439	0	0
T87	0	996	0	0
T88	0	917	0	0