Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1056047	0	0
ctrl_rd_A	2147483647	23339	0	0
intr_enable_rd_A	2147483647	21511	0	0
ovrd_rd_A	2147483647	22278	0	0
timeout_ctrl_rd_A	2147483647	22652	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1056047	0	0
T6	297948	9303	0	0
T7	857	0	0	0
T8	249309	0	0	0
T9	329847	0	0	0
T10	770127	0	0	0
T11	708661	0	0	0
T12	264374	10238	0	0
T15	185521	0	0	0
T19	50693	0	0	0
T21	0	6446	0	0
T22	0	4823	0	0
T24	190714	0	0	0
T29	0	4296	0	0
T30	0	14036	0	0
T31	0	4295	0	0
T32	0	12735	0	0
T33	0	15313	0	0
T34	0	12879	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	23339	0	0
T6	297948	495	0	0
T7	857	0	0	0
T8	249309	0	0	0
T9	329847	0	0	0
T10	770127	0	0	0
T11	708661	0	0	0
T12	264374	0	0	0
T15	185521	0	0	0
T19	50693	0	0	0
T22	0	581	0	0
T24	190714	0	0	0
T29	0	627	0	0
T32	0	1208	0	0
T90	0	501	0	0
T91	0	342	0	0
T92	0	1014	0	0
T93	0	616	0	0
T94	0	843	0	0
T95	0	1300	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21511	0	0
T1	955649	5	0	0
T2	1030	0	0	0
T3	142209	0	0	0
T4	18515	0	0	0
T5	592984	0	0	0
T6	297948	386	0	0
T7	857	0	0	0
T8	249309	0	0	0
T9	329847	0	0	0
T10	770127	0	0	0
T22	0	432	0	0
T29	0	580	0	0
T32	0	1233	0	0
T90	0	441	0	0
T91	0	301	0	0
T92	0	1116	0	0
T93	0	485	0	0
T94	0	746	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22278	0	0
T6	297948	456	0	0
T7	857	0	0	0
T8	249309	0	0	0
T9	329847	0	0	0
T10	770127	0	0	0
T11	708661	0	0	0
T12	264374	0	0	0
T15	185521	0	0	0
T19	50693	0	0	0
T22	0	481	0	0
T24	190714	0	0	0
T29	0	628	0	0
T32	0	1344	0	0
T90	0	535	0	0
T91	0	447	0	0
T92	0	1046	0	0
T93	0	532	0	0
T94	0	959	0	0
T95	0	1222	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22652	0	0
T6	297948	412	0	0
T7	857	0	0	0
T8	249309	0	0	0
T9	329847	0	0	0
T10	770127	0	0	0
T11	708661	0	0	0
T12	264374	0	0	0
T15	185521	0	0	0
T19	50693	0	0	0
T22	0	590	0	0
T24	190714	0	0	0
T29	0	637	0	0
T32	0	1374	0	0
T90	0	510	0	0
T91	0	353	0	0
T92	0	1015	0	0
T93	0	600	0	0
T94	0	761	0	0
T95	0	1359	0	0